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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
Product Specification
DS083 (v4.7) November 5, 2007
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Module 1: Introduction and Overview
10 pages * * * * * * Summary of Features General Description Architecture IP Core and Reference Support Device/Package Combinations and Maximum I/O Ordering Information
Module 3: DC and Switching Characteristics
57 pages * * * * * * * Electrical Characteristics Performance Characteristics Switching Characteristics Pin-to-Pin Output Parameter Guidelines Pin-to-Pin Input Parameter Guidelines DCM Timing Parameters Source-Synchronous Switching Characteristics
Module 2: Functional Description
60 pages * * * * * Functional Description: RocketIOTM X Multi-Gigabit Transceiver Functional Description: RocketIO Multi-Gigabit Transceiver Functional Description: Processor Block Functional Description: PowerPCTM 405 Core Functional Description: FPGA
Input/Output Blocks (IOBs) Digitally Controlled Impedance (DCI) On-Chip Differential Termination Configurable Logic Blocks (CLBs) 3-State Buffers CLB/Slice Configurations 18-Kb Block SelectRAMTM Resources 18-Bit x 18-Bit Multipliers Global Clock Multiplexer Buffers Digital Clock Manager (DCM)
Module 4: Pinout Information
302 pages * * Pin Definitions Pinout Tables
FG256/FGG256 Wire-Bond Fine-Pitch BGA Package FG456/FGG456 Wire-Bond Fine-Pitch BGA Package FG676/FGG676 Wire-Bond Fine-Pitch BGA Package FF672 Flip-Chip Fine-Pitch BGA Package FF896 Flip-Chip Fine-Pitch BGA Package FF1148 Flip-Chip Fine-Pitch BGA Package FF1152 Flip-Chip Fine-Pitch BGA Package FF1517 Flip-Chip Fine-Pitch BGA Package FF1696 Flip-Chip Fine-Pitch BGA Package FF1704 Flip-Chip Fine-Pitch BGA Package
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Routing Configuration
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
(c) 2002-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Product Specification
DS083 (v4.7) November 5, 2007
Summary of Virtex-II ProTM / Virtex-II Pro X Features
* High-Performance Platform FPGA Solution, Including - Up to twenty RocketIOTM or RocketIO X embedded Multi-Gigabit Transceivers (MGTs) - Up to two IBM PowerPCTM RISC processor blocks Based on Virtex-IITM Platform FPGA Technology - Flexible logic resources - SRAM-based in-system configuration - Active Interconnect technology SelectRAMTM+ memory hierarchy Dedicated 18-bit x 18-bit multiplier blocks High-performance clock management circuitry SelectI/OTM-Ultra technology XCITE Digitally Controlled Impedance (DCI) I/O
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Virtex-II Pro / Virtex-II Pro X family members and resources are shown in Table 1.
Table 1: Virtex-II Pro / Virtex-II Pro X FPGA Family Members
CLB (1 = 4 slices = max 128 bits) Logic Cells(2) 3,168 6,768 11,088 20,880 22,032 30,816 43,632 53,136 74,448 74,448 99,216 Slices 1,408 3,008 4,928 9,280 9,792 13,696 19,392 23,616 33,088 33,088 44,096 Max Distr RAM (Kb) 44 94 154 290 306 428 606 738 1,034 1,034 1,378 Block SelectRAM+ 18 Kb Max Block Blocks RAM (Kb) 12 28 44 88 88 136 192 232 328 308 444 216 504 792 1,584 1,584 2,448 3,456 4,176 5,904 5,544 7,992 DCMs 4 4 4 8 8 8 8 8 8 8 12
Device (1) XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Notes:
1. 2. 3. 4.
RocketIO Transceiver Blocks 4 4 8 8 8(4) 8 0(3), 8, or 12 0(3) or 16 16 or 20 20(4) 0(3) or 20
PowerPC Processor Blocks 0 1 1 2 1 2 2 2 2 2 2
18 X 18 Bit Multiplier Blocks 12 28 44 88 88 136 192 232 328 308 444
Maximum User I/O Pads 204 348 396 564 552 644 804 852 996 992 1,164
-7 speed grade devices are not available in Industrial grade. Logic Cell (1) 4-input LUT + (1)FF + Carry Logic These devices can be ordered in a configuration without RocketIO transceivers. See Table 3 for package configurations. Virtex-II Pro X devices equipped with RocketIO X transceiver cores.
RocketIO X Transceiver Features (XC2VPX20 and XC2VPX70 Only)
* Variable-Speed Full-Duplex Transceiver (XC2VPX20) Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates. - Includes specific baud rates used by various standards, as listed in Table 4, Module 2. Fixed-Speed Full-Duplex Tranceiver (XC2VPX70) Operating at 4.25 Gb/s Baud Transfer Rate. Eight or Twenty Transceiver Modules on an FPGA, Depending upon Device Monolithic Clock Synthesis and Clock Recovery - Eliminates the need for external components * * Automatic Lock-to-Reference Function Programmable Serial Output Differential Swing - 200 mV to 1600 mV, peak-peak - Allows compatibility with other serial system voltage levels Programmable Pre-emphasis Levels 0 to 500% Telecom/Datacom Support Modes - "x8" and "x10" clocking/data paths - 64B/66B clocking support
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(c) 2002-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview Internal Loopback Modes for Testing Operability Programmable Comma Detection - Allows for any protocol - Allows for detection of any 10-bit character 8B/10B and 64B/66B Encoding Blocks
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Programmable Receiver Equalization Internal AC Coupling On-Chip 50 Termination - Eliminates the need for external termination resistors Pre- and Post-Driver Serial and Parallel TX-to-RX
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RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70)
* * * * Full-Duplex Serial Transceiver (SERDES) Capable of Baud Rates from 600 Mb/s to 3.125 Gb/s 100 Gb/s Duplex Data Rate (20 Channels) Monolithic Clock Synthesis and Clock Recovery (CDR) Fibre Channel, 10G Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and Infiniband-Compliant Transceivers 8-, 16-, or 32-bit Selectable Internal FPGA Interface 8B /10B Encoder and Decoder (optional) * * * * * * * * 50 /75 on-chip Selectable Transmit and Receive Terminations Programmable Comma Detection Channel Bonding Support (from 2 to 20 Channels) Rate Matching via Insertion/Deletion Characters Four Levels of Selectable Pre-Emphasis Five Levels of Output Differential Voltage Per-Channel Internal Loopback Modes 2.5V Transceiver Supply Voltage
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PowerPC RISC Processor Block Features (All Except XC2VP2)
* * * * * * * Embedded 300+ MHz Harvard Architecture Block Low Power Consumption: 0.9 mW/MHz Five-Stage Data Path Pipeline Hardware Multiply/Divide Unit Thirty-Two 32-bit General Purpose Registers 16 KB Two-Way Set-Associative Instruction Cache 16 KB Two-Way Set-Associative Data Cache * Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB) Dedicated On-Chip Memory (OCM) Interface Supports IBM CoreConnectTM Bus Architecture Debug and Trace Support Timer Facilities
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Virtex-II Pro Platform FPGA Technology (All Devices)
* SelectRAM+ Memory Hierarchy - Up to 8 Mb of True Dual-Port RAM in 18 Kb block SelectRAM+ resources - Up to 1,378 Kb of distributed SelectRAM+ resources - High-performance interfaces to external memory Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 88,192 internal registers/latches with Clock Enable - Up to 88,192 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state busing High-Performance Clock Management Circuitry - Up to twelve Digital Clock Manager (DCM) modules * Precise clock de-skew
* * Flexible frequency synthesis High-resolution phase shifting
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- 16 global clock multiplexer buffers in all parts Active Interconnect Technology - Fourth-generation segmented routing structure - Fast, predictable routing delay, independent of fanout - Deep sub-micron noise immunity benefits SelectIOTM-Ultra Technology - Up to 1,164 user I/Os - Twenty-two single-ended standards and ten differential standards - Programmable LVCMOS sink/source current (2 mA to 24 mA) per I/O - XCITE Digitally Controlled Impedance (DCI) I/O - PCI/ PCI-X support (1) - Differential signaling * 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers * On-chip differential termination * Bus LVDS I/O
1. Refer to XAPP653 for more information.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview - Readback capability Supported by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Integrated VHDL and Verilog design flows - ChipScopeTM Integrated Logic Analyzer 0.13 m Nine-Layer Copper Process with 90 nm High-Speed Transistors 1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 Compatible Boundary-Scan Logic Support Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Standard 1.00 mm Pitch. Wire-Bond BGA Devices Available in Pb-Free Packaging (www.xilinx.com/pbfree) Each Device 100% Factory Tested
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HyperTransport (LDT) I/O with current driver buffers Built-in DDR input and output registers
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Proprietary high-performance SelectLink technology for communications between Xilinx devices * High-bandwidth data path * Double Data Rate (DDR) link * Web-based HDL generation methodology SRAM-Based In-System Configuration - Fast SelectMAPTM configuration - Triple Data Encryption Standard (DES) security option (bitstream encryption) - IEEE 1532 support - Partial reconfiguration - Unlimited reprogrammability
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General Description
The Virtex-II Pro and Virtex-II Pro X families contain platform FPGAs for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU blocks in Virtex-II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The leading-edge 0.13 m CMOS nine-layer copper process and Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays.
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Block SelectRAM+ memory modules provide large 18 Kb storage elements of True Dual-Port RAM. Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, and coarse- and fine-grained clock phase shifting.
A new generation of programmable routing resources called Active Interconnect Technology interconnects all these elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. The overall programmable interconnection is hierarchical and supports high-speed designs. All programmable elements, including the routing resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements.
Architecture
Array Overview
Virtex-II Pro and Virtex-II Pro X devices are user-programmable gate arrays with various configurable elements and embedded blocks optimized for high-density and high-performance system designs. Virtex-II Pro devices implement the following functionality: * Embedded high-speed serial transceivers enable data bit rate up to 3.125 Gb/s per channel (RocketIO) or 6.25 Gb/s (RocketIO X). Embedded IBM PowerPC 405 RISC processor blocks provide performance up to 400 MHz. SelectIO-Ultra blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs. Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources.
Features
This section briefly describes Virtex-II Pro / Virtex-II Pro X features. For more details, refer to Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description.
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RocketIO / RocketIO X MGT Cores
The RocketIO and RocketIO X Multi-Gigabit Transceivers are flexible parallel-to-serial and serial-to-parallel embedded transceiver cores used for high-bandwidth interconnection between buses, backplanes, or other subsystems. Multiple user instantiations in an FPGA are possible, providing up to 100 Gb/s (RocketIO) or 170 Gb/s (RocketIO X) of full-duplex raw data transfer. Each channel can be operated at a maximum data transfer rate of 3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X).
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview Separate instruction and data cache units, both two-way set-associative and non-blocking - Eight words (32 bytes) per cache line - 16 KB array Instruction Cache Unit (ICU), 16 KB array Data Cache Unit (DCU) - Operand forwarding during instruction cache line fill - Copy-back or write-through DCU strategy - Doubleword instruction fetch from cache improves branch latency Virtual mode memory management unit (MMU) - Translation of the 4 GB logical address space into physical addresses - Software control of page replacement strategy - Supports multiple simultaneous page sizes ranging from 1 KB to 16 MB OCM controllers provide dedicated interfaces between Block SelectRAM+ memory and processor block instruction and data paths for high-speed access PowerPC timer facilities - 64-bit time base - Programmable interval timer (PIT) - Fixed interval timer (FIT) - Watchdog timer (WDT) Debug Support - Internal debug mode - External debug mode - Debug Wait mode - Real Time Trace debug mode - Enhanced debug support with logical operators - Instruction trace and trace-back support - Forward or backward trace Two hardware interrupt levels support Advanced power management support -
Each RocketIO or RocketIO X core implements the following technology: * * * Serializer and deserializer (SERDES) Monolithic clock synthesis and clock recovery (CDR) 10 Gigabit Attachment Unit Interface (XAUI) Fibre Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express, Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48 compatibility(1) 8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X) selectable FPGA interface 8B/10B (RocketIO) or 8B/10B and 64B/66B (RocketIO X) encoder and decoder with bypassing option on each channel Channel bonding support (two to twenty channels) - Elastic buffers for inter-chip deskewing and channel-to-channel alignment Receiver clock recovery tolerance of up to 75 non-transitioning bits 50 (RocketIO X) or 50 /75 selectable (RocketIO) on-chip transmit and receive terminations Programmable comma detection and word alignment Rate matching via insertion/deletion characters Automatic lock-to-reference function Programmable pre-emphasis support Per-channel serial and parallel transmitter-to-receiver internal loopback modes Optional transmit and receive data inversion Cyclic Redundancy Check support (RocketIO only)
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PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sustained rate of one instruction per cycle. On-chip instruction and data cache reduce design complexity and improve system throughput. The PPC405 features include: * PowerPC RISC CPU - Implements the PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications - Thirty-two 32-bit general purpose registers (GPRs) - Static branch prediction - Five-stage pipeline with single-cycle execution of most instructions, including loads/stores - Unaligned and aligned load/store support to cache, main memory, and on-chip memory - Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) - Enhanced string and multiple-word handling - Big/little endian operation support Storage Control * *
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows: * * Input block with an optional single data rate (SDR) or double data rate (DDR) register Output block with an optional SDR or DDR register and an optional 3-state buffer to be driven directly or through an SDR or DDR register Bidirectional block (any combination of input and output configurations)
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These registers are either edge-triggered D-type flip-flops or level-sensitive latches. IOBs support the following single-ended I/O standards: * * * * LVTTL, LVCMOS (3.3V,(2) 2.5V, 1.8V, and 1.5V) PCI-X compatible (133 MHz and 66 MHz) at 3.3V (3) PCI compliant (66 MHz and 33 MHz) at 3.3V (3) GTL and GTLP
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1. Refer to Table 4, Module 2 for detailed information about RocketIO and RocketIO X transceiver compatible protocols. 2. Refer to XAPP659 for more information. 3. Refer to XAPP653 for more information. DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview mized for operations based on the block SelectRAM+ content on one port. The 18 x 18 multiplier can be used independently of the block SelectRAM+ resource. Read/multiply/accumulate operations and DSP filter structures are extremely efficient. Both the SelectRAM+ memory and the multiplier resource are connected to four switch matrices to access the general routing resources.
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HSTL (1.5V and 1.8V, Class I, II, III, and IV) SSTL (1.8V and 2.5V, Class I and II)
The DCI I/O feature automatically provides on-chip termination for each single-ended I/O standard. The IOB elements also support the following differential signaling I/O standards: * * * * * LVDS and Extended LVDS (2.5V) BLVDS (Bus LVDS) ULVDS LDT LVPECL (2.5V)
Global Clocking
The DCM and global clock multiplexer buffers provide a complete solution for designing high-speed clock schemes. Up to twelve DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. Fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clock output frequency equal to a fractional or integer multiple of the input clock frequency. For exact timing parameters, see Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. Virtex-II Pro devices have 16 global clock MUX buffers, with up to eight clock nets per quadrant. Each clock MUX buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. Each DCM can send up to four of its clock outputs to global clock buffers on the same edge. Any global clock pin can drive any DCM on the same edge.
Two adjacent pads are used for each differential pair. Two or four IOBs connect to one switch matrix to access the routing resources. On-chip differential termination is available for LVDS, LVDS Extended, ULVDS, and LDT standards.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers. Each slice is equivalent and contains: * * * * * * * Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Wide function capability Fast carry look-ahead chain Horizontal cascade chain (OR gate)
The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-bit shift registers, or as 16-bit distributed SelectRAM+ memory. In addition, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources.
Routing Resources
The IOB, CLB, block SelectRAM+, multiplier, and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance of high-speed designs. There are a total of 16 global clock lines, with eight available per quadrant. In addition, 24 vertical and horizontal long lines per row or column, as well as massive secondary and local routing resources, provide fast interconnect. Virtex-II Pro buffered interconnects are relatively unaffected by net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources for each row or column include: * * * * 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions)
Block SelectRAM+ Memory
The block SelectRAM+ memory resources are 18 Kb of True Dual-Port RAM, programmable from 16K x 1 bit to 512 x 36 bit, in various depth and width configurations. Each port is totally synchronous and independent, offering three "read-during-write" modes. Block SelectRAM+ memory is cascadable to implement large embedded storage blocks. Supported memory configurations for dual-port and single-port modes are shown in Table 2. Table 2: Dual-Port and Single-Port Configurations 16K x 1 bit 8K x 2 bits 4K x 4 bits 2K x 9 bits 1K x 18 bits 512 x 36 bits
Boundary Scan 18 X 18 Bit Multipliers
A multiplier block is associated with each SelectRAM+ memory block. The multiplier block is a dedicated 18 x 18-bit 2s complement signed multiplier, and is optiBoundary-scan instructions and associated data registers support a standard methodology for accessing and configuring Virtex-II Pro devices, complying with IEEE standards 1149.1 and 1532. A system mode and a test mode are
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores and Integrated Bus Analyzer (IBA) cores, along with the ChipScope Pro Analyzer software, provide a complete solution for accessing and verifying user designs within Virtex-II Pro devices.
implemented. In system mode, a Virtex-II Pro device will continue to function while executing non-test Boundary-Scan instructions. In test mode, Boundary-Scan test instructions control the I/O pins for testing purposes. The Virtex-II Pro Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instructions are also supported.
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution. In addition to the existing FPGA fabric cores, the list below shows some of the currently available hardware and software intellectual properties specially developed for Virtex-II Pro / Virtex-II Pro X by Xilinx. Each IP core is modular, portable, Real-Time Operating System (RTOS) independent, and CoreConnect compatible for ease of design migration. Refer to www.xilinx.com/ipcenter for the latest and most complete list of cores.
Configuration
Virtex-II Pro / Virtex-II Pro devices are configured by loading the bitstream into internal configuration memory using one of the following modes: * * * * * Slave-serial mode Master-serial mode Slave SelectMAP mode Master SelectMAP mode Boundary-Scan mode (IEEE 1532)
Hardware Cores
* * * * * * * * * * Bus Infrastructure cores (arbiters, bridges, and more) Memory cores (DDR, Flash, and more) Peripheral cores (UART, IIC, and more) Networking cores (ATM, Ethernet, and more) Boot code Test code Device drivers Protocol stacks RTOS integration Customized board support package
A Data Encryption Standard (DES) decryptor is available on-chip to secure the bitstreams. One or two triple-DES key sets can be used to optionally encrypt the configuration data. The Xilinx System Advanced Configuration Enviornment (System ACE) family offers high-capacity and flexible solution for FPGA configuration as well as program/data storage for the processor. See DS080, System ACE CompactFlash Solution for more information.
Software Cores
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II Pro / Virtex-II Pro configuration memory can be read back for verification. Along with the configuration data, the contents of all flip-flops and latches, distributed SelectRAM+, and block SelectRAM+ memory resources can be read back. This capability is useful for real-time debugging.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Virtex-II Pro / Virtex-II Pro X Device/Package Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with 1.0 mm pitch. In addition to traditional wire-bond interconnect (FG/FGG packages), flip-chip interconnect (FF packages) is used in some of the BGA offerings. Flip-chip interconnect construction supports more I/Os than are possible in wire-bond versions of similar packages, providing a high pin count and excellent power dissipation. The device/package combination table (Table 3) details the maximum number of user I/Os and RocketIO / RocketIO X MGTs for each device and package using wire-bond or flip-chip technology. The FF1148 and FF1696 packages have no RocketIO transceivers bonded out. Extra SelectIO-Ultra resources occupy available pins in these packages, resulting in a higher user I/O count. These packages are available for the XC2VP40, XC2VP50, and XC2VP100 devices only. The I/Os per package count includes all user I/Os except the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, and RSVD), VBATT, and the RocketIO / RocketIO X transceiver pins.
Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
Package (1) Pitch (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Notes:
1. 2. 3. Wirebond packages FG256, FG456, and FG676 are also available in Pb-free versions FGG256, FGG456, and FGG676. See Virtex-II Pro Ordering Examples for details on how to order. Virtex-II Pro X device is equipped with RocketIO X transceiver cores. The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
FG256/ FGG256
1.00 17 x 17 140 / 4 140 / 4
FG456/ FGG456
1.00 23 x 23 156 / 4 248 / 4 248 / 8
FG676
1.00 26 x 26
FF672
1.00 27 x 27 204 / 4 348 / 4 396 / 8
FF896
1.00 31 x 31
FF1152
1.00 35 x 35
FF1148
1.00 35 x 35
FF1517
1.00 40 x 40
FF1704
1.00 42.5 x 42.5
FF1696
1.00 42.5 x 42.5
396 / 8 556 / 8 552 / 8 (2) 564 / 8
404 / 8
416 / 8 416 / 8
556 / 8
644 / 8 692 / 12 692 / 16 804 / 0 (3) 812 / 0 (3) 852 / 16 964 / 16 996 / 20 992 / 20 (2) 1,040 / 20 1,164 / 0 (3)
Maximum Performance
Maximum performance of the RocketIO / RocketIO X transceiver and the PowerPC processor block varies, depending on package style and speed grade. See Table 4 for details. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics contains the rest of the FPGA fabric performance parameters. Table 4: Maximum RocketIO / RocketIO X Transceiver and Processor Block Performance
Speed Grade Device RocketIO X Transceiver FlipChip (FF) RocketIO Transceiver FlipChip (FF) RocketIO Transceiver Wirebond (FG) PowerPC Processor Block
Notes:
1. 2. 3. -7 speed grade devices are not available in Industrial grade. IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than 300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, "PowerPC 405 Clock Macro for -7(C) and -6(I) Speed Grade Dual-Processor Devices." Refer to Table 1 to identify dual-processor devices. XC2VPX70 is only available at fixed 4.25 Gb/s baud rate.
-7 (1) N/A 3.125 2.5 400 (2)
-6 6.25 (3) 3.125 2.5 350 (2)
-5 4.25 (3) 2.0 2.0 300
Units Gb/s Gb/s Gb/s MHz
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Virtex-II Pro Ordering Examples
Virtex-II Pro ordering examples are shown in Figure 1 (flip-chip package) and Figure 2 (Pb-free wire-bond package).
Example: XC2VP40 -7 FF 1152 C
Device Type Speed Grade (-5, -6, -7*) Temperature Range: C = Commercial (Tj = 0C to +85C) I = Industrial* (Tj = -40C to +100C) Number of Pins
*NOTE: -7 devices not available in Industrial grade.
Package Type
DS083_02_062104
Figure 1: Virtex-II Pro Ordering Example, Flip-Chip Package
Example: XC2VP40 -6 FG G 676 I
Device Type Speed Grade (-5, -6, -7*) Temperature Range: C = Commercial (Tj = 0C to +85C) I = Industrial* (Tj = -40C to +100C) Number of Pins Pb-Free Package Type
*NOTE: -7 devices not available in Industrial grade.
DS083-1_02b_062104
Figure 2: Virtex-II Pro Ordering Example, Pb-Free Wire-Bond Package
Virtex-II Pro X Ordering Example
A Virtex-II Pro X ordering example is shown in Figure 3.
Example: XC2VPX20 -6 FF 896 C
Device Type Speed Grade (-5, -6) Temperature Range: C = Commercial (Tj = 0C to +85C) I = Industrial* (Tj = -40C to +100C) Number of Pins Package Type
DS083_02a_092705
Figure 3: Virtex-II Pro X Ordering Example, Flip-Chip Package
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Revision History
This section records the change history for this module of the data sheet. Date 01/31/02 06/13/02 09/03/02 09/27/02 11/20/02 01/20/03 03/24/03 08/25/03 12/10/03 02/19/04 Version 1.0 2.0 2.1 2.2 2.3 2.4 2.4.1 2.4.2 3.0 3.1 Initial Xilinx release. New Virtex-II Pro family members. New timing parameters per speedsfile v1.62. Updates to Table 1 and Table 3. Processor Block information added to Table 4. In Table 1, correct max number of XC2VP30 I/Os to 644. Add bullet items for 3.3V I/O features. * * * * * * * * * * 03/09/04 06/30/04 11/17/04 03/01/05 06/20/05 09/15/05 3.1.1 4.0 4.1 4.2 4.3 4.4 * In Table 3, add FG676 package option for XC2VP20, XC2VP30, and XC2VP40. Remove FF1517 package option for XC2VP40. Correct number of single-ended I/O standards from 19 to 22. Correct minimum RocketIO serial speed from 622 Mbps to 600 Mbps. Add footnote referring to XAPP659 to callout for 3.3V I/O standards on page 4. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, are released to Production status. Table 1: Corrected number of RocketIO transceiver blocks for XC2VP40. Section Virtex-II Pro Platform FPGA Technology (All Devices): Updated number of differential standards supported from six to ten. Section Input/Output Blocks (IOBs): Added text stating that differential termination is available for LVDS, LVDS Extended, ULVDS, and LDT standards. Figure 1: Added note stating that -7 devices are not available in Industrial grade. Recompiled for backward compatibility with Acrobat 4 and above. No content changes. Revision
Merged in DS110-1 (Module 1 of Virtex-II Pro X data sheet). Added information on available Pb-free packages. No changes in Module 1 for this revision. Table 3: Corrected number of RocketIO transceivers for XC2VP7-FG456. No changes in Module 1 for this revision. * * Changed all instances of 10.3125 Gb/s (RocketIO transceiver maximum bit rate) to 6.25 Gb/s. Changed all instances of 412.5 Gb/s (RocketIO X transceiver maximum multi-channel raw data transfer rate) to 250 Gb/s. Changed XC2VPX70 variable baud rate specification to fixed-rate operation at 4.25 Gb/s. Changed maximum performance for -7 Virtex-II Pro X MGT (Table 4) to N/A.
10/10/05
4.5
* *
03/05/07 11/05/07
4.6 4.7
No changes in Module 1 for this revision. Updated copyright notice and legal disclaimer.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules: * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview (Module 1) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description (Module 2) * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics (Module 3) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information (Module 4)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Product Specification
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Virtex-II Pro(1) Array Functional Description
These User Guides are available:
DCM
RocketIO or RocketIO X Multi-Gigabit Transceiver
*
* *
CLB Multipliers and Block SelectRAM CLB
Processor Block
*
For detailed descriptions of PPC405 embedded core programming models and internal core operations, see PowerPC Processor Reference Guide and PowerPC 405 Processor Block Reference Guide. For detailed RocketIO transceiver digital/analog design considerations, see RocketIO Transceiver User Guide. For detailed RocketIO X transceiver digital/analog design considerations, see RocketIO X Transceiver User Guide, For detailed descriptions of the FPGA fabric (CLB, IOB, DCM, etc.), see Virtex-II Pro Platform FPGA User Guide.
CLB CLB
Configurable Logic
All of the documents above, as well as a complete listing and description of Xilinx-developed Intellectual Property cores for Virtex-II Pro, are available on the Xilinx website.
Contents of This Module
* * * * * * Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT) Functional Description: RocketIO Multi-Gigabit Transceiver (MGT) Functional Description: Processor Block Functional Description: Embedded PowerPC 405 Core Functional Description: FPGA Revision History
SelectIO-Ultra
DS083-1_01_050304
Figure 1: Virtex-II Pro Generic Architecture Overview This module describes the following VirtexTM-II Pro functional components, as shown in Figure 1: * Embedded RocketIOTM (up to 3.125 Gb/s) or RocketIO X (up to 6.25 Gb/s) Multi-Gigabit Transceivers (MGTs) Processor blocks with embedded IBM PowerPCTM 405 RISC CPU core (PPC405) and integration circuitry. FPGA fabric based on Virtex-II architecture.
Virtex-II Pro Compared to Virtex-II Devices
Virtex-II Pro devices are built on the Virtex-II FPGA architecture. Most FPGA features are identical to Virtex-II devices. Major differences are described below: * * The Virtex-II Pro FPGA family is the first to incorporate embedded PPC405 and RocketIO/RocketIO X cores. VCCAUX, the auxiliary supply voltage, is 2.5V instead of 3.3V as for Virtex-II devices. Advanced processing at 0.13 m has resulted in a smaller die, faster speed, and lower power consumption. Virtex-II Pro devices are neither bitstream-compatible nor pin-compatible with Virtex-II devices. However, Virtex-II designs can be compiled into Virtex-II Pro devices. On-chip input LVDS differential termination is available. SSTL3, AGP-2X/AGP, LVPECL_33, LVDS_33, and LVDSEXT_33 standards are not supported. The open-drain output pin TDO does not have an internal pull-up resistor.
* *
Virtex-II Pro User Guides
Virtex-II Pro User Guides cover theory of operation in more detail, and include implementation details, primitives and attributes, command/instruction sets, and many HDL code examples where appropriate. All parameter specifications are given only in Module 3 of this Data Sheet. *
* * *
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
(c) 2002-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO X multi-gigabit transceiver. For an in-depth discussion of the RocketIO X MGT, including digital and analog design considerations, refer to the RocketIO X Transceiver User Guide. See Table 7, page 17, for a summary of the differences between the RocketIO X PMA/PCS and the RocketIO PMA/PCS. Figure 4, page 3 shows a high-level block diagram of the RocketIO X transceiver and its FPGA interface signals. Table 1: Communications Standards Supported by RocketIO X Transceiver (2) Mode
SONET OC-48 PCI Express Infiniband XAUI (10-Gb Ethernet) XAUI (10-Gb Fibre Channel) Aurora (Xilinx protocol) Custom Mode
RocketIO X Overview
Either eight or twenty RocketIO X MGTs are available on the XC2VPX20 and XC2VPX70 devices, respectively. The XC2VPX20 MGT is designed to operate at any baud rate in the range of 2.488 Gb/s to 6.25 Gb/s per channel. This includes specific baud rates used by various standards as listed in Table 1. The XC2VPX70 MGT operates at a fixed 4.25 Gb/s per channel. The RocketIO X MGT consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the 6.25 Gb/s serializer/deserializer (SERDES), TX/RX buffers, clock generator, and clock recovery circuitry. The RocketIO X PCS has been significantly updated relative to the RocketIO PCS. In addition to the existing RocketIO PCS features, the RocketIO X PCS features 64B/66B encoder/decoder/scrambler/descrambler and SONET compatibility.
Channels (Lanes) (1)
1 1, 2, 4, 8, 16 1, 4, 12 4 4 1, 2, 3, 4,... 1, 2, 3, 4,...
I/O Bit Rate (Gb/s)
2.488 2.5 2.5 3.125 3.1875 2.488 to 6.25 2.488 to 6.25
Notes: 1. One channel is considered to be one transceiver.
2. XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
PMA
Transmitter Output
The RocketIO X transceiver is implemented in Current Mode Logic (CML). A CML transmitter output consists of transistors configured as shown in Figure 2. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of the driver, VP and VN, sink current, with one leg always sinking more current than its complement. The CML output consists of a differential pair with 50 source resistors. The signal swing is created by switching the current in a common-source differential pair.
Transmitter Termination
On-chip termination is provided at the transmitter, eliminating the need for external termination. The output driver and termination are powered by VTTX at 1.5V. This configuration uses a CML approach with 50 termination to TXP and TXN as shown in Figure 3.
VTTX (1.5V) 50 50 TXP
VP VN
VP - VN
=
V DATA
TXN
CML Output Driver
DS083-2_66_052104 ug083_34_050704
Figure 3: RocketIO X Transmit Termination
Figure 2: CML Output Configuration
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
PACKAGE PINS
AVCCAUXTX VTRX 2.5V Termination Supply RX
FPGA FABRIC MULTI-GIGABIT TRANSCEIVER CORE
Power Down POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN 64B/66B Descrambler Deserializer Comma Detect Realign 8B/10B Decoder RXDATA[63:0] RX Elastic Buffer RXNOTINTABLE[7:0] RXDISPERR[7:0] RXCHARISK[7:0] RXCHARISCOMMA[7:0] RXRUNDISP[7:0] RXBUFSTATUS[1:0] ENCHANSYNC CHBONDDONE CHBONDI[4:0] CHBONDO[4:0] RXLOSSOFSYNC[1:0] RXCLKCORCNT[2:0] TXBUFERR
Gear Box Scrambler
RXP RXN
Post Driver Serial Loopback Path
Pre-Driver Loopback Path
Clock Manager
Parallel Loopback Path
64B/66B Block Sync
Channel Bonding and Clock Correction
64B/66B Decoder
64B/66B Encoder TX FIFO 8B/10B Encoder
TXDATA[63:0] TXBYPASS8B10B[7:0] TXCHARISK[7:0] TXCHARDISPMODE[7:0] TXCHARDISPVAL[7:0] TXKERR[7:0] TXRUNDISP[7:0] TXPOLARITY TXINHIBIT LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLKP BREFCLKN RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 PMAINIT PMAREGADDR[5:0] PMAREGDATAIN[7:0] PMAREGRW PMAREGSTROBE PMARXLOCKSEL[1:0] PMARXLOCK REFCLKBSEL RXBLCOKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH[1:0] RXDECC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH[1:0] RXSLIDE TXDATAWIDTH[1:0] TXENC64B66BUSE TXENC8B10BUSE TXFORCECRCERR TXGEARBOX64B66BUSE TXINTDATAWIDTH[1:0] TXSCRAM64B66BUSE TXOUTCLK
DS083-2_37_050704
TXP TXN
Serializer
Output Polarity
GNDA AVCCAUXRX VTTX
TX/RX GND 1.5V Termination Supply TX
Clock / Reset
PMA Attribute Load
Figure 4: RocketIO X Transceiver Block Diagram
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description This clock is presented to the FPGA fabric at 1/10, 1/16, 1/20, 1/32, or 1/40 the incoming data rate depending on the operating mode. A sufficient number of transitions must be present in the data stream for CDR to work properly. The CDR circuit is guaranteed to work with 8B/10B and 64B/66B encoding. Further, CDR requires approximately 5,000 transitions upon power-up to guarantee locking to the incoming data rate. Once lock is achieved, up to 75 missing transitions can be tolerated before lock to the incoming data stream is lost. Another feature of CDR is its ability to accept an external precision reference clock, REFCLK, which either acts to clock incoming data or to assist in synchronizing the derived RXRECCLK. For further clarity, the TXUSRCLK is used to clock data from the FPGA fabric to the TX FIFO. The FIFO depth accounts for the slight phase difference between these two clocks. If the clocks are locked in frequency, then the FIFO acts much like a pass-through buffer. The receiver can be configured to reverse the RXP and RXN inputs. This can be useful in the event that printed circuit board traces have been reversed.
Output Swing and Emphasis
The output swing and emphasis levels are fully programmable. Each is controlled via attributes at configuration, and can be modified via the PMA attribute programming bus. The programmable output swing control can adjust the differential peak-to-peak output level between 200 mV and 1600 mV. With emphasis, the differential voltage swing is boosted to create a stronger rising or falling waveform. This method compensates for high frequency loss in the transmission media that would otherwise limit the magnitude of this waveform. Lossy transmission lines cause the dissipation of electrical energy. This emphasis technique extends the distance that signals can be driven down lossy line media and increases the signal-to-noise ratio at the receiver. Emphasis can be described from two perspectives, additive to the smaller voltage (VSM) (pre-emphasis) or subtractive from the larger voltage (VLG) (de-emphasis). The resulting benefits in compensating for channel loss are identical. It is simply a relative way of specifying the effect at the transmitter. The equations for calculating pre-emphasis as a percentage and dB are as follows:
Pre-Emphasis% = ((VLG-VSM) / VSM) x 100 Pre-EmphasisdB = 20 log(VLG/VSM)
Receiver Lock Control
The CDR circuits will lock to the reference clock automatically if the data is not present. For proper operation, the frequency of the reference clock must be within 100 ppm of the nominal frequency. During normal operation, the receiver PLL automatically locks to incoming data (when present) or to the local reference clock (when data is not present). This is the default configuration for all primitives. This function can be overridden via the PMARXLOCKSEL port When receive PLL lock is forced to the local reference, phase information from the incoming data stream is ignored. Data continues to be sampled, but synchronous to the local reference rather than relative to edges in the data stream.
The equations for calculating de-emphasis as a percentage and dB are as follows:
De-Emphasis% = (VLG - VSM) / VLG) x 100 De-EmphasisdB = 20 log(VSM/VLG)
The pre-emphasis amount can be programmed in discrete steps between 0% and 500%. The de-emphasis amount can be programmed in discrete steps between 0% and 83%.
Serializer
The serializer multiplies the reference frequency provided on REFCLK by 10, 16, 20, 32, or 40, depending on the operation mode. The multiplication of the clock is achieved by using an embedded PLL. Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs. The electrical connection of TXP and TXN can be interchanged through configuration. This option can be controlled by an input (TXPOLARITY) at the FPGA transmitter interface.
Receive Equalization
In addition to transmit emphasis, the RocketIO X MGT provides a programmable active receive equalization feature to further compensate the effects of channel attenuation at high frequencies. By adjusting RXFER, the right amount of equalization can be added to reverse the signal degradation caused by a printed circuit board, a backplane, or a line/switch card. RXFER can be set through software configuration or the PMA Attribute Bus.
Deserializer
Synchronous serial data reception is facilitated by a clock and data recovery (CDR) circuit. This circuit uses a fully monolithic Phase Lock Loop (PLL), which does not require any external components. The CDR circuit extracts both phase and frequency from the incoming data stream. The derived clock, RXRECCLK, is generated and locked to as long as it remains within the specified component range.
Receiver Termination
On-chip termination is provided at the receiver, eliminating the need for external termination. The receiver termination supply (VTRX) is the center tap of differential termination to
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description using a CML (high-side) termination to an active supply of 1.8V - 2.5V. For DC coupling of two Virtex-II Pro X devices, a 1.5V CML termination for VTRX is recommended.
RXP and RXN as shown in Figure 5. This supports multiple termination styles, including high-side, low-side, and differential (floating or active). This configuration supports receiver termination compatible to Virtex-II Pro devices,
VTRX 50 RXP 50
RXN
ds083-2_35_050704
Figure 5: RocketIO X Receive Termination
PCS
Fabric Data Interface
Internally, the PCS operates in either 2-byte mode (16/20 bits) or 4-byte mode (32/40 bits). When in 2-byte mode, the FPGA fabric interface can either be 1, 2, or 4 bytes wide. When in 4-byte mode, the FPGA fabric interface can either be 4 or 8 bytes wide. When accompanied by the predefined modes of the PMA, the user thus has a large combination of protocols and data rates from which to choose. USRCLK2 clocks data on the fabric side, while USRCLK clocks data on the PCS side. This creates distinct USRCLK/USRCLK2 frequency ratios for different combinations of fabric and internal data widths. Table 2 summarizes the USRCLK2-to-USRCLK ratios for the different possible combinations of data widths. Table 2: Clock Ratios for Various Data Widths
Frequency Ratio of USRCLK:USRCLK2 Fabric Data Width 2-Byte Internal Data Width 4-Byte Internal Data Width
No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other clock that is not tied to either of these clocks. When RXUSRCLK and RXUSRCLK2 have different frequencies, each edge of the slower clock is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and TXUSRCLK2.
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of data to the transmitter. Each character can be either 8 bits or 10 bits wide. If 8-bit data is applied, the additional inputs become control signals for the 8B/10B encoder. When the 8B/10B encoder is bypassed, the 10-bit character order is generated as follows: TXCHARDISPMODE[0] (first bit transmitted) TXCHARDISPVAL[0] TXDATA[7:0] (last bit transmitted is TXDATA[0])
64B/66B Encoder/Decoder
The RocketIO X PCS features a 64B/66B encoder/decoder, scrambler/descrambler, and gearbox functions that can be bypassed as needed. The encoder is compliant with IEEE 802.3ae specifications.
1 byte 2 byte 4 byte 8 byte
1:2 (1) 1:1 2:1 (1) N/A
N/A N/A 1:1 2:1 (1)
Scrambler/Gearbox
The bypassable scrambler operates on the read side of the transmit FIFO. The scrambler uses the following generator polynomial to scramble 64B/66B payload data: G(x) = 1 + x39 + x58 The scrambler works in conjunction with the gearbox, which frames 64B/66B data for the PMA. The gearbox should always be enabled when using the 64B/66B protocal.
Notes: 1. Each edge of slower clock must align with falling edge of faster clock.
As a general guide, use 2-byte internal data width mode when the serial speed is below 5 Gb/s, and 4-byte internal data width mode when the serial speed is greater than 5 Gb/s. In 2-byte mode, the PCS processes 4-byte data every other byte.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description decoding all data and K-characters, the decoder has several extra features. The decoder separately detects both "disparity errors" and "out-of-band" errors. A disparity error is the reception of 10-bit character that exists within the 8B/10B table but has an incorrect disparity. An out-of-band error is the reception of a 10-bit character that does not exist within the 8B/10B table. It is possible to obtain an out-of-band error without having a disparity error. The proper disparity is always computed for both legal and illegal characters. The current running disparity is available at the RXRUNDISP signal. The 8B/10B decoder performs a unique operation if out-of-band data is detected. If out-of-band data is detected, the decoder signals the error and passes the illegal 10-bits through and places them on the outputs. This can be used for debugging purposes if desired. The decoder also signals the reception of one of the 12 valid K-characters. In addition, a programmable comma detect is included. The comma detect signal registers a comma on the receipt of any comma+, comma-, or both. Since the comma is defined as a 7-bit character, this includes several out-of-band characters. Another option allows the decoder to detect only the three defined commas (K28.1, K28.5, and K28.7) as comma+, comma-, or both. In total, there are six possible options, three for valid commas and three for "any comma." Note that all bytes (1, 2, 4, or 8) at the RX FPGA interface each have their own individual 8B/10B indicators (K-character, disparity error, out-of-band error, current running disparity, and comma detect).
Power Sequencing
Disparity Control
The 8B/10B encoder is initialized with a negative running disparity. Unique control allows forcing the current running disparity state. TXRUNDISP signals its current running disparity. This may be useful in those cases where there is a need to manipulate the initial running disparity value. Bits TXCHARDISPMODE and TXCHARDISPVAL control the generation of running disparity before each byte. For example, the transceiver can generate the sequence
K28.5+ K28.5+ K28.5- K28.5-
or
K28.5- K28.5- K28.5+ K28.5+
by specifying inverted running disparity for the second and fourth bytes.
Transmit FIFO
Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations up to one clock cycle are allowable. The FIFO has a depth of four. Overflow or underflow conditions are detected and signaled at the interface. Bypassing of this FIFO is programmable.
8B/10B Encoder
Note: In the RocketIO transceiver, the most-significant byte is sent first; in the RocketIO X transceiver, the least-significant byte is sent first.
A bypassable 8B/10B encoder is included. The encoder uses the same 256 data characters and 12 control characters used by Gigabit Ethernet, Fibre Channel, and InfiniBand. The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per character applied, and generates a 10 bit character for transmission. If the K-character signal is High, the data is encoded into one of the twelve possible K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded as standard data. If the K-character input is High, and a user applies other than one of the twelve possible combinations, TXKERR indicates the error.
Receiver Buffer
The receiver includes buffers (FIFOs) in the datapath. This section gives the reasons for including the buffers and outlines their operation. The receiver buffer is required for two reasons: * Clock correction to accommodate the slight difference in frequency between the recovered clock RXRECCLK and the internal FPGA user clock RXUSRCLK Channel bonding to allow realignment of the input stream to ensure proper alignment of data being read through multiple transceivers
*
8B/10B Decoder
Note: In the RocketIO transceiver, the most-significant byte is sent first; in the RocketIO X transceiver, the least-significant byte is sent first.
The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read pointer for clock correction and channel bonding. Comma Detection Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the transceiver recognizes up to two 10-bit preprogrammed characters. Upon detection of the character or characters, the comma detect output is driven high and the data is synchronously aligned. If a comma is detected and the data is aligned, no further alignment alteration takes place. If a comma is received and realignment is necessary, the data is realigned and an indi-
An optional 8B/10B decoder is included. A programmable option allows the decoder to be bypassed. When the 8B/10B decoder is bypassed, the 10-bit character order is, for example, RXCHARISK[0] RXRUNDISP[0] RXDATA[7:0] (first bit received) (last bit received is RXDATA[0])
The decoder uses the same table that is used for Gigabit Ethernet, Fibre Channel, and InfiniBand. In addition to
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock correction logic corrects for this by decrementing the read pointer to reread a repeatable byte sequence. This is shown in the middle buffer, Figure 6, where the solid read pointer decrements to the value represented by the dashed pointer. By decrementing the read pointer instead of incrementing it in the usual fashion, the buffer is partially refilled. The transceiver design will repeat a single repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver may repeat the same sequence multiple times until the buffer is refilled to the desired extent. Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer will fill up over time. The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA fabric byte stream. This is shown in the bottom buffer, Figure 6, where the solid read pointer increments to the value represented by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design will skip a single byte sequence when necessary to partially empty a buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver may also skip two consecutive removable byte sequences in one step to further empty the buffer when necessary. These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or other sequence comprised of special values that occur in the gaps separating packets of meaningful data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction. Channel Bonding
Buffer less than half -full (emptying) Repeatable sequence Write
cation is given at the receiver interface. The realignment indicator is a distinct output. The transceiver continuously monitors the data for the presence of the 10-bit character(s). Upon each occurrence of a 10-bit character, the data is checked for word alignment. If comma detect is disabled, the data is not aligned to any particular pattern. The programmable option allows a user to align data on comma+, comma-, both, or a unique user-defined and programmed sequence. Comma detection has been expanded beyond 10-bit symbol detection and alignment to include 8-bit symbol detection and alignment for 16-, 20-, 32-, and 40-bit paths. The ability to detect symbols, and then either align to 1-word, 2-word, or 4-word boundaries is included. The RXSLIDE input allows the user to "slide" or "slip" the alignment by one bit in each 16-, 20-, 32- and 40-bit mode at any time for SONET applications. Comma detection can be bypassed when needed. Clock Correction RXRECCLK (the recovered clock) reflects the data rate of the incoming data. RXUSRCLK defines the rate at which the FPGA fabric consumes the data. Ideally, these rates are identical. However, since the clocks typically have different sources, one of the clocks will be faster than the other. The receiver buffer accommodates this difference between the clock rates. See Figure 6.
Read RXUSRCLK Write RXRECCLK
"Nominal" condition: buffer half-full
Read Write
Read
Some gigabit I/O standards such as Infiniband specify the use of multiple transceivers in parallel for even higher data rates. Words of data are split into bytes, with each byte sent over a separate channel (transceiver). See Figure 7. The top half of the figure shows the transmission of words split across four transceivers (channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels. The bottom-left portion of Figure 7 shows the initial situation in the FPGA's receivers at the other end of the four channels. Due to variations in transmission delay--especially if the channels are routed through repeaters--the FPGA fabric might not correctly assemble the bytes into complete words. The bottom-left illustration shows the incorrect assembly of data words PQPP, QRQQ, RSRR, and so forth. To support correction of this misalignment, the data stream includes special byte sequences that define corresponding points in the several channels. In the bottom half of Figure 7, the shaded "P" bytes represent these special characters. Each receiver recognizes the "P" channel bond-
Buffer more than half-full (filling up)
Removable sequence
DS083-2_15_100901
Figure 6: Clock Correction in Receiver Nominally, the buffer is always half full. This is shown in the top buffer, Figure 6, where the shaded area represents buffered data not yet read. Received data is inserted via the write pointer under control of RXRECCLK. The FPGA fabric reads data via the read pointer under control of RXUSRCLK. The half full/half empty condition of the buffer gives a cushion for the differing clock rates. This operation continues indefinitely, regardless of whether or not "meaningful" data is being received. When there is no meaningful data to be received, the incoming data will consist of IDLE characters or other padding.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
ing character, and remembers its location in the buffer. At some point, one transceiver designated as the master instructs all the transceivers to align to the channel bonding character "P" (or to some location relative to the channel bonding character). After this operation, words transmitted to the FPGA fabric are properly aligned: RRRR, SSSS, TTTT, and so forth, as shown in the bottom-right portion of Figure 7. To ensure that the channels remain properly aligned following the channel bonding operation, the master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers.
In Transmitters:
Full word SSSS sent over four channels, one byte per channel
PQRS T PQRS T PQRS T PQRS T
Channel (lane) 0 Channel (lane) 1 Channel (lane) 2 Channel (lane) 3
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is frequency-locked to its read pointer (REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK. A simple FIFO suffices for this purpose. A FIFO depth of four will permit reliable operation with simple detection of overflow or underflow, which could occur if the clocks are not frequency-locked.
Read RXUSRCLK
PQRS T PQRS T PQRS T PQRS T
In Receivers:
Read RXUSRCLK
PQRS T PQRS T PQRS T PQRS T
Before channel bonding
After channel bonding
DS083-2_16_010202
Figure 7: Channel Bonding (Alignment)
RocketIO X Configuration
This section outlines functions that can be selected or controlled by configuration. Xilinx implementation software supports the transceiver primitives shown in Table 3. Table 3: Supported RocketIO X Transceiver Primitives Primitive
GT10_CUSTOM GT10_OC48_1 GT10_OC48_2 GT10_OC48_4 GT10_PCI_EXPRESS_1 GT10_PCI_EXPRESS_2 GT10_PCI_EXPRESS_4 GT10_INFINIBAND_1 GT10_INFINIBAND_2 GT10_INFINIBAND_4
Description
Fully customizable by user SONET OC-48, 1-byte data path SONET OC-48, 2-byte data path SONET OC-48, 4-byte data path PCI Express, 1-byte data path PCI Express, 2-byte data path PCI Express, 4-byte data path Infiniband, 1-byte data path Infiniband, 2-byte data path Infiniband, 4-byte data path
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description receiver elastic buffer and resets all receiver registers and the decoder. When the signals TXRESET or RXRESET are asserted High, the PCS is in reset. After TXRESET or RXRESET are deasserted, the PCS takes five clocks to come out of reset for each clock domain. The PMA configuration vector is not affected during this reset, so the PMA speed, filter settings, and so on, all remain the same. Also, the PMA internal pipeline is not affected and continues to operate in normal fashion.
Other RocketIO X Features and Notes
Loopback
In order to facilitate testing without having the need to either apply patterns or measure data at GHz rates, four programmable loop-back features are available. The first option, serial loopback, is available in two modes: pre-driver and post-driver. * The pre-driver mode loops back to the receiver without going through the output driver. In this mode, TXP and TXN are not driven and therefore need not be terminated. The post-driver mode is the same as the RocketIO loopback. In this mode, TXP and TXN are driven and must be properly terminated.
Power
The transceiver voltage regulator circuits must not be shared with any other supplies (including FPGA supplies VCCINT, VCCO, VCCAUX, and VREF). Voltage regulators can be shared among transceiver power supplies of the same voltage, but each supply pin must still have its own separate passive filtering network. All RocketIO transceivers in the FPGA, whether instantiated in the design or not, must be connected to power and ground. Unused transceivers can be powered by any 1.5V or 2.5V source, and passive filtering is not required. The Power Down feature is controlled by the transceiver's POWERDOWN input pin. Any given transceiver that is not instantiated in the design is automatically set to the POWERDOWN state by the Xilinx ISE development software. The Power Down pin on the FPGA package has no effect on the MGT.
*
The third option, parallel loopback, checks the digital circuitry. When parallel loopback is enabled, the serial loopback path is disabled. However, the transmitter outputs remain active, and data can be transmitted. If TXINHIBIT is asserted, TXP is forced to 0 until TXINHIBIT is de-asserted. The fourth option, repeater loopback, allows received data to be transmitted without going through the FPGA fabric.
Reset
The receiver and transmitter have their own synchronous reset inputs. The transmitter reset, TXRESET, recenters the transmission FIFO and resets all transmitter registers and the encoder. The receiver reset, RXRESET, recenters the
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: RocketIO Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO multi-gigabit transceiver. For an in-depth discussion of the RocketIO MGT, including digital and analog design considerations, refer to the RocketIO Transceiver User Guide. Figure 10, page 11 shows a high-level block diagram of the RocketIO transceiver and its FPGA interface signals.
Table 4: Protocols Supported by RocketIO Transceiver
RocketIO Overview
Up to twenty RocketIO MGTs are available. The MGT is designed to operate at any baud rate in the range of 622 Mb/s to 3.125 Gb/s per channel. This includes specific baud rates used by various standards as listed in Table 4. The RocketIO MGT consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the 3.125 Gb/s serializer/deserializer (SERDES), TX/RX buffers, clock generator, and clock recovery circuitry. The PCS contains the bypassable 8B/10B encoder/ decoder, elastic buffers, and Cyclic Redundancy Check (CRC) units. The encoder and decoder handle the 8B/10B coding scheme. The elastic buffers support the clock correction (rate matching) and channel bonding features. The CRC units perform CRC generation and checking. See Table 7, page 17, for a summary of the differences between the RocketIO X PMA/PCS and the RocketIO PMA/PCS.
Mode
Channels (Lanes) (1)
I/O Bit Rate (Gb/s)
1.06
Fibre Channel
1
2.12 3.1875 (2)
Gigabit Ethernet 10Gbit Ethernet Infiniband Aurora Custom Protocol
1 4 1, 4, 12 1, 2, 3, 4, ... 1, 2, 3, 4, ...
1.25 3.125 2.5 0.622 - 3.125 up to 3.125
Notes: 1. One channel is considered to be one transceiver. 2. Virtex-II Pro MGT can support the 10G Fibre Channel data rates of 3.1875 Gb/s across 6" of standard FR-4 PCB and one connector (Molex 74441 or equivalent) with a bit error rate of 10-12 or better.
PMA
Transmitter Output
The RocketIO transceiver is implemented in Current Mode Logic (CML). A CML transmitter output consists of transistors configured as shown in Figure 8. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of the driver, VP and VN, sink current, with one leg always sinking more current than its complement. The CML output consists of a differential pair with 50 (or, optionally, 75) source resistors. The signal swing is created by switching the current in a common-source differential pair.
Transmitter Termination
On-chip termination is provided at the transmitter, eliminating the need for external termination. The output driver and termination are powered by VTTX. This configuration uses a CML approach with selectable 50 or 75 termination to TXP and TXN as shown in Figure 9.
VTTX 50/75 50/75 TXP
VP VN
VP - VN
=
V DATA TXN
ug083_33_061504
CML Output Driver
Figure 9: RocketIO Transmit Termination
DS083-2_66_052104
Figure 8: CML Output Configuration
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
PACKAGE PINS
AVCCAUXRX VTRX 2.5V RX Termination Supply RX
MULTI-GIGABIT TRANSCEIVER CORE
Power Down
FPGA FABRIC
POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN CRC Check RXCHECKINGCRC RXCRCERR RXDATA[15:0] RXDATA[31:16]
RXP RXN Deserializer Comma Detect Realign 8B/10B Decoder
RX Elastic Buffer
RXNOTINTABLE[3:0] RXDISPERR[3:0] RXCHARISK[3:0] RXCHARISCOMMA[3:0] RXRUNDISP[3:0] RXBUFSTATUS[1:0] ENCHANSYNC CHBONDDONE CHBONDI[3:0] CHBONDO[3:0] RXLOSSOFSYNC RXCLKCORCNT TXBUFERR TXFORCECRCERR TXDATA[15:0] TXDATA[31:16]
Clock Manager
Parallel Loopback Path
Serial Loopback Path
Channel Bonding and Clock Correction
TXP TXN
TX FIFO Serializer Output Polarity
8B/10B Encoder
CRC
TXBYPASS8B10B[3:0] TXCHARISK[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXKERR[3:0] TXRUNDISP[3:0] TXPOLARITY TXINHIBIT LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLK BREFCLK2 RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2
DS083-2_04_090402
GNDA AVCCAUXTX VTTX
TX/RX GND 2.5V TX Termination Supply TX
Figure 10: RocketIO Transceiver Block Diagram
Output Swing and Pre-emphasis
The output swing and pre-emphasis levels of the RocketIO MGTs are fully programmable. Each is controlled via attributes at configuration, but can be modified via partial reconfiguration. The programmable output swing control can adjust the differential output level between 400 mV and 800 mV in four increments of 100 mV.
With pre-emphasis, the differential voltage swing is boosted to create a stronger rising waveform. This method compensates for high-frequency loss in the transmission media that would otherwise limit the magnitude of this waveform. Lossy transmission lines cause the dissipation of electrical energy. This pre-emphasis technique extends the distance that signals can be driven down lossy line media and increases the signal-to-noise ratio at the receiver.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description tee locking to the incoming data rate. Once lock is achieved, up to 75 missing transitions can be tolerated before lock to the incoming data stream is lost. The CDR circuit is guaranteed to work with 8B/10B encoding. Another feature of CDR is its ability to accept an external precision reference clock, REFCLK, which either acts to clock incoming data or to assist in synchronizing the derived RXRECCLK. For further clarity, the TXUSRCLK is used to clock data from the FPGA fabric to the TX FIFO. The FIFO depth accounts for the slight phase difference between these two clocks. If the clocks are locked in frequency, then the FIFO acts much like a pass-through buffer. The receiver can be configured to reverse the RXP and RXN inputs. This can be useful in the event that printed circuit board traces have been reversed.
Serializer
The serializer multiplies the reference frequency provided on REFCLK by 20. The multiplication of the clock is achieved by using an embedded PLL. Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs. The electrical connection of TXP and TXN can be interchanged through configuration. This option can be controlled by an input (TXPOLARITY) at the FPGA transmitter interface.
Deserializer
The serial transceiver input is locked to the input data stream through Clock and Data Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate. The derived clock, RXRECCLK, is generated and locked to as long as it remains within the specified component range. This clock is presented to the FPGA fabric at 1/20 the incoming data rate. A sufficient number of transitions must be present in the data stream for CDR to work properly. CDR requires approximately 5,000 transitions upon power-up to guaran-
Receiver Termination
On-chip termination is provided at the receiver, eliminating the need for external termination. The receiver includes programmable on-chip termination circuitry for 50 (default) or 75 impedance, as shown in Figure 11.
VTRX 50/75 RXP 50/75
RXN
ds083-2_36_111704
Figure 11: RocketIO Receive Termination
PCS
Fabric Data Interface
Internally, the PCS operates in 2-byte mode (16/20 bits). The FPGA fabric interface can either be 1, 2, or 4 bytes wide. When accompanied by the predefined modes of the PMA, the user thus has a large combination of protocols and data rates from which to choose. USRCLK2 clocks data on the fabric side, while USRCLK clocks data on the PCS side. This creates distinct USRCLK/USRCLK2 frequency ratios for different combinations of fabric and internal data widths. Table 5 summarizes the USRCLK2 to USRCLK ratios for the three fabric data widths. No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other clock that is not tied to either of these clocks. When RXUSRCLK and RXUSRCLK2 have different frequencies, each edge of the slower clock is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and TXUSRCLK2.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per character applied, and generates a 10 bit character for transmission. If the K-character signal is High, the data is encoded into one of the twelve possible K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded as standard data. If the K-character input is High, and a user applies other than one of the twelve possible combinations, TXKERR indicates the error.
Table 5: Clock Ratios for Various Data Widths
Fabric Data Width Frequency Ratio of USRCLK:USRCLK2
1-byte 2-byte 4-byte
1:2 (1) 1:1 2:1 (1)
Notes: 1. Each edge of slower clock must align with falling edge of faster clock.
8B/10B Decoder
Note: In the RocketIO transceiver, the most-significant byte is sent first; in the RocketIO X transceiver, the least-significant byte is sent first.
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of data to the transmitter. Each character can be either 8 bits or 10 bits wide. If 8-bit data is applied, the additional inputs become control signals for the 8B/10B encoder. When the 8B/10B encoder is bypassed, the 10-bit character order is generated as follows: TXCHARDISPMODE[0] (first bit transmitted) TXCHARDISPVAL[0] TXDATA[7:0] (last bit transmitted is TXDATA[0])
An optional 8B/10B decoder is included. A programmable option allows the decoder to be bypassed. When the 8B/10B decoder is bypassed, the 10-bit character order is, for example, RXCHARISK[0] RXRUNDISP[0] RXDATA[7:0] (first bit received) (last bit received is RXDATA[0])
Disparity Control
The 8B/10B encoder is initialized with a negative running disparity. Unique control allows forcing the current running disparity state. TXRUNDISP signals its current running disparity. This may be useful in those cases where there is a need to manipulate the initial running disparity value. Bits TXCHARDISPMODE and TXCHARDISPVAL control the generation of running disparity before each byte. For example, the transceiver can generate the sequence
K28.5+ K28.5+ K28.5- K28.5-
The decoder uses the same table that is used for Gigabit Ethernet, Fibre Channel, and InfiniBand. In addition to decoding all data and K-characters, the decoder has several extra features. The decoder separately detects both "disparity errors" and "out-of-band" errors. A disparity error is the reception of 10-bit character that exists within the 8B/10B table but has an incorrect disparity. An out-of-band error is the reception of a 10-bit character that does not exist within the 8B/10B table. It is possible to obtain an out-of-band error without having a disparity error. The proper disparity is always computed for both legal and illegal characters. The current running disparity is available at the RXRUNDISP signal. The 8B/10B decoder performs a unique operation if out-of-band data is detected. If out-of-band data is detected, the decoder signals the error and passes the illegal 10-bits through and places them on the outputs. This can be used for debugging purposes if desired. The decoder also signals the reception of one of the 12 valid K-characters. In addition, a programmable comma detect is included. The comma detect signal registers a comma on the receipt of any comma+, comma-, or both. Since the comma is defined as a 7-bit character, this includes several out-of-band characters. Another option allows the decoder to detect only the three defined commas (K28.1, K28.5, and K28.7) as comma+, comma-, or both. In total, there are six possible options, three for valid commas and three for "any comma." Note that all bytes (1, 2, or 4) at the RX FPGA interface each have their own individual 8B/10B indicators (K-character, disparity error, out-of-band error, current running disparity, and comma detect).
Power Sequencing
or
K28.5- K28.5- K28.5+ K28.5+
by specifying inverted running disparity for the second and fourth bytes.
Transmit FIFO
Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations up to one clock cycle are allowable. The FIFO has a depth of four. Overflow or underflow conditions are detected and signaled at the interface. Bypassing of this FIFO is programmable.
8B/10B Encoder
Note: In the RocketIO transceiver, the most-significant byte is sent first; in the RocketIO X transceiver, the least-significant byte is sent first.
A bypassable 8B/10B encoder is included. The encoder uses the same 256 data characters and 12 control characters used by Gigabit Ethernet, Fibre Channel, and InfiniBand.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description corrects for this by decrementing the read pointer to reread a repeatable byte sequence. This is shown in the middle buffer, Figure 12, where the solid read pointer decrements to the value represented by the dashed pointer.
Read RXUSRCLK Write RXRECCLK
Receiver Buffer
The receiver includes buffers (FIFOs) in the datapath. This section gives the reasons for including the buffers and outlines their operation. The receiver buffer is required for two reasons: * Clock correction to accommodate the slight difference in frequency between the recovered clock RXRECCLK and the internal FPGA user clock RXUSRCLK Channel bonding to allow realignment of the input stream to ensure proper alignment of data being read through multiple transceivers
*
"Nominal" condition: buffer half-full
Read Write
The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read pointer for clock correction and channel bonding. Comma Detection Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the transceiver recognizes up to two 10-bit preprogrammed characters. Upon detection of the character or characters, the comma detect output is driven high and the data is synchronously aligned. If a comma is detected and the data is aligned, no further alignment alteration takes place. If a comma is received and realignment is necessary, the data is realigned and an indication is given at the receiver interface. The realignment indicator is a distinct output. The transceiver continuously monitors the data for the presence of the 10-bit character(s). Upon each occurrence of a 10-bit character, the data is checked for word alignment. If comma detect is disabled, the data is not aligned to any particular pattern. The programmable option allows a user to align data on comma+, comma-, both, or a unique user-defined and programmed sequence. Clock Correction RXRECCLK (the recovered clock) reflects the data rate of the incoming data. RXUSRCLK defines the rate at which the FPGA fabric consumes the data. Ideally, these rates are identical. However, since the clocks typically have different sources, one of the clocks will be faster than the other. The receiver buffer accommodates this difference between the clock rates. See Figure 12. Nominally, the buffer is always half full. This is shown in the top buffer, Figure 12, where the shaded area represents buffered data not yet read. Received data is inserted via the write pointer under control of RXRECCLK. The FPGA fabric reads data via the read pointer under control of RXUSRCLK. The half full/half empty condition of the buffer gives a cushion for the differing clock rates. This operation continues indefinitely, regardless of whether or not "meaningful" data is being received. When there is no meaningful data to be received, the incoming data will consist of IDLE characters or other padding. If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock correction logic
DS083 (v4.7) November 5, 2007 Product Specification
Read
Buffer less than half -full (emptying) Repeatable sequence Write
Buffer more than half-full (filling up)
Removable sequence
DS083-2_15_100901
Figure 12: Clock Correction in Receiver By decrementing the read pointer instead of incrementing it in the usual fashion, the buffer is partially refilled. The transceiver design will repeat a single repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver may repeat the same sequence multiple times until the buffer is refilled to the desired extent. Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer will fill up over time. The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA fabric byte stream. This is shown in the bottom buffer, Figure 12, where the solid read pointer increments to the value represented by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design will skip a single byte sequence when necessary to partially empty a buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver may also skip two consecutive removable byte sequences in one step to further empty the buffer when necessary. These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or other sequence comprised of special values that occur in the gaps separating packets of meaningful data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction. Channel Bonding Some gigabit I/O standards such as Infiniband specify the use of multiple transceivers in parallel for even higher data rates. Words of data are split into bytes, with each byte sent over a separate channel (transceiver). See Figure 13.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
The top half of the figure shows the transmission of words split across four transceivers (channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels. The bottom-left portion of Figure 13 shows the initial situation in the FPGA's receivers at the other end of the four channels. Due to variations in transmission delay--especially if the channels are routed through repeaters--the FPGA fabric might not correctly assemble the bytes into complete words. The bottom-left illustration shows the incorrect assembly of data words PQPP, QRQQ, RSRR, and so forth.
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is frequency-locked to its read pointer (REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK. A simple FIFO suffices for this purpose. A FIFO depth of four will permit reliable operation with simple detection of overflow or underflow, which could occur if the clocks are not frequency-locked.
RocketIO Configuration
This section outlines functions that can be selected or controlled by configuration. Xilinx implementation software supports 16 transceiver primitives, as shown in Table 6. Each of the primitives in Table 6 defines default values for the configuration attributes, allowing some number of them to be modified by the user. Refer to the RocketIO Transceiver User Guide for more details. Table 6: Supported RocketIO MGT Protocol Primitives
GT_CUSTOM GT_FIBRE_CHAN_1 Fully customizable by user Fibre Channel, 1-byte data path Fibre Channel, 2-byte data path Fibre Channel, 4-byte data path Gigabit Ethernet, 1-byte data path Gigabit Ethernet, 2-byte data path Gigabit Ethernet, 4-byte data path 10-gigabit Ethernet, 1-byte data path 10-gigabit Ethernet, 2-byte data path 10-gigabit Ethernet, 4-byte data path Infiniband, 1-byte data path Infiniband, 2-byte data path Infiniband, 4-byte data path 1-byte data path 2-byte data path 4-byte data path
In Transmitters:
Full word SSSS sent over four channels, one byte per channel
PQRS T PQRS T PQRS T PQRS T
Channel (lane) 0 Channel (lane) 1 Channel (lane) 2 Channel (lane) 3
Read RXUSRCLK
PQRS T PQRS T PQRS T PQRS T
In Receivers:
Read RXUSRCLK
PQRS T
GT_FIBRE_CHAN_2 GT_FIBRE_CHAN_4 GT_ETHERNET_1
PQRS T PQRS T PQRS T
GT_ETHERNET_2 GT_ETHERNET_4 GT_XAUI_1
Before channel bonding
After channel bonding
DS083-2_16_010202
GT_XAUI_2 GT_XAUI_4 GT_INFINIBAND_1 GT_INFINIBAND_2 GT_INFINIBAND_4 GT_AURORA_1 (1) GT_AURORA_2 (1) GT_AURORA_4 (1)
Figure 13: Channel Bonding (Alignment) To support correction of this misalignment, the data stream includes special byte sequences that define corresponding points in the several channels. In the bottom half of Figure 13, the shaded "P" bytes represent these special characters. Each receiver recognizes the "P" channel bonding character, and remembers its location in the buffer. At some point, one transceiver designated as the master instructs all the transceivers to align to the channel bonding character "P" (or to some location relative to the channel bonding character). After this operation, words transmitted to the FPGA fabric are properly aligned: RRRR, SSSS, TTTT, and so forth, as shown in the bottom-right portion of Figure 13. To ensure that the channels remain properly aligned following the channel bonding operation, the master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers.
Notes: 1. For more information on the Aurora protocol, visit
http://www.xilinx.com.
Other RocketIO Features and Notes
CRC
The RocketIO transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, FibreChannel, and Gigabit Ethernet. On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC. For Gigabit Ethernet and FibreChannel, transmitter
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description remain active, and data can be transmitted. If TXINHIBIT is asserted, TXP is forced to 0 until TXINHIBIT is de-asserted.
CRC may adjust certain trailing bytes to generate the required running disparity at the end of the packet. On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards as above. The CRC logic also supports a user mode, with a simple data packet stucture beginning and ending with user-defined SOP and EOP characters.
Reset
The receiver and transmitter have their own synchronous reset inputs. The transmitter reset recenters the transmission FIFO, and resets all transmitter registers and the 8B/10B decoder. The receiver reset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B encoder. Neither reset has any effect on the PLLs.
Loopback
In order to facilitate testing without having the need to either apply patterns or measure data at GHz rates, two programmable loop-back features are available. One option, serial loopback, places the gigabit transceiver into a state where transmit data is directly fed back to the receiver. An important point to note is that the feedback path is at the output pads of the transmitter. This tests the entirety of the transmitter and receiver. The second option, parallel loopback, checks the digital circuitry. When parallel loopback is enabled, the serial loopback path is disabled. However, the transmitter outputs
Power
All RocketIO transceivers in the FPGA, whether instantiated in the design or not, must be connected to power and ground. Unused transceivers can be powered by any 2.5V source, and passive filtering is not required.
Power Down
The Power Down module is controlled by the transceiver's POWERDOWN input pin. The Power Down pin on the FPGA package has no effect on the transceiver.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
RocketIO and RocketIO X Feature Comparison
Table 7 summarizes the major differences between the RocketIO and RocketIO X MGTs. The RocketIO X Transceiver User Guide has more details, including a design migration guide in the Appendix. Table 7: RocketIO PMA versus RocketIO X PMA RocketIO X Transceiver PCS Features: FPGA interface Coding support Gearbox/scrambler support CRC Support Half rate PMA Features: Baud rate Reference clock frequency tolerance Reference clock multiplier Max run length Receive equalization Output swing (differential p-p) Pre-emphasis Slew rate control Termination AC coupling capacitor Transmit supply voltage (AVCCAUXTX) Receive supply voltage (AVCCAUXRX) PMA configuration support Others: JTAG support Process technology Available packages Input only 0.13 m Flip-chip only None 0.25 m Flip-chip and wire-bond 2.488 Gb/s - 6.25 Gb/s (2) 350 PPM x16, x20, x32, x40 75 Built-in analog linear, programmable 200 mV to 1600 mV, programmable 0% to 500%, programmable 2 selectable levels On-chip internal, 50 On-chip internal. Can be AC- or DC-coupled externally 2.5V 1.5V, 1.8V (1) Direct, dynamic, and partial configuration 622 Mb/s - 3.125 Gb/s 100 PPM x20 75 None 800 mV to 1600 mV, programmable 4 selectable levels from 10% to 33% None On-chip internal, 50/75 selectable None 2.5V 2.5V Partial configuration 1, 2, 4, and 8 byte width 8B/10B and 64B/66B bypassable Yes No No 1, 2, and 4 byte width 8B/10B bypassable N/A Yes Yes RocketIO Transceiver
Notes: 1. AVCCAUXRX for RocketIO X MGT is 1.5V (nominal) for 8B/10B-encoded data. For all other encoding protocols, AVCCAUXRX is 1.8V (nominal). 2. The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description core to operate at 300+ MHz while maintaining low power consumption. Specially designed interface logic integrates the core with the surrounding CLBs, block RAMs, and general routing resources. Up to four Processor Blocks can be available in a single Virtex-II Pro device. The embedded PPC405 core implements the PowerPC User Instruction Set Architecture (UISA), user-level registers, programming model, data types, and addressing modes for 32-bit fixed-point operations. 64-bit operations, auxiliary processor operations, and floating-point operations are trapped and can be emulated in software. Most of the PPC405 core features are compatible with the specifications for the PowerPC Virtual Environment Architecture (VEA) and Operating Environment Architecture (OEA). They also provide a number of optimizations and extensions to the lower layers of the PowerPC Architecture. The full architecture of the PPC405 is defined by the PowerPC Embedded Environment and PowerPC UISA documentation, available from IBM.
Functional Description: Processor Block
This section briefly describes the interfaces and components of the Processor Block. The subsequent section, Functional Description: Embedded PowerPC 405 Core beginning on page 20, offers a summary of major PPC405 core features. For an in-depth discussion on both the Processor Block and PPC405, see tthe PowerPC Processor Reference Guide and the PowerPC 405 Processor Block Reference Guide available on the Xilinx website at http://www.xilinx.com.
Processor Block Overview
Figure 14 shows the internal architecture of the Processor Block.
CPU-FPGA Interfaces
BRAM
BRAM
On-Chip Memory (OCM) Controllers
Control
Introduction
The OCM controllers serve as dedicated interfaces between the block RAMs in the FPGA fabric (see 18 Kb Block SelectRAM+ Resources, page 44) and OCM signals available on the embedded PPC405 core. The OCM signals on the PPC405 core are designed to provide very quick access to a fixed amount of instruction and data memory space. The OCM controller provides an interface to both the 64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit Data-Side Block RAM (DSBRAM). The designer can choose to implement: * * * * ISBRAM only DSBRAM only Both ISBRAM and DSBRAM No ISBRAM and no DSBRAM
OCM Controller
BRAM
OCM Controller
PPC 405 Core
BRAM
FPGA CLB Array
Interface Logic
Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface
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Figure 14: Processor Block Architecture Within the Virtex-II Pro Processor Block, there are four components: * * * * Embedded IBM PowerPC 405-D5 RISC CPU core On-Chip Memory (OCM) controllers and interfaces Clock/control interface logic CPU-FPGA Interfaces
One of OCM's primary advantages is that it guarantees a fixed latency of execution for a higher level of determinism. Additionally, it reduces cache pollution and thrashing, since the cache remains available for caching code from other memory resources. Typical applications for DSOCM include scratch-pad memory, as well as use of the dual-port feature of block RAM to enable bidirectional data transfer between processor and FPGA. Typical applications for ISOCM include storage of interrupt service routines.
Functional Features
Common Features * * Separate Instruction and Data memory interface between processor core and BRAMs in FPGA Dedicated interface to Device Control Register (DCR) bus for ISOCM and DSOCM
Embedded PowerPC 405 RISC Core
The PowerPC 405D5 core is a 0.13 m implementation of the IBM PowerPC 405D4 core. The advanced process technology enables the embedded PowerPC 405 (PPC405)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description non-Processor Block user signals. Longlines and hex lines travel across the Processor Block both vertically and horizontally, allowing signals to route through the Processor Block.
* *
* *
*
Single-cycle and multi-cycle mode option for I-side and D-side interfaces Single cycle = one CPU clock cycle; multi-cycle = minimum of two and maximum of eight CPU clock cycles FPGA configurable DCR addresses within DSOCM and ISOCM. Independent 16 MB logical memory space available within PPC405 memory map for each of the DSOCM and ISOCM. The number of block RAMs in the device might limit the maximum amount of OCM supported. Maximum of 64K and 128K bytes addressable from DSOCM and ISOCM interfaces, respectively, using address outputs from OCM directly without additional decoding logic. 32-bit Data Read bus and 32-bit Data Write bus Byte write access to DSBRAM support Second port of dual port DSBRAM is available to read/write from an FPGA interface 22-bit address to DSBRAM port 8-bit DCR Registers: DSCNTL, DSARC Three alternatives to write into DSBRAM: BRAM initialization, CPU, FPGA H/W using second port
Processor Local Bus (PLB) Interfaces
The PPC405 core accesses high-speed system resources through PLB interfaces on the instruction and data cache controllers. The PLB interfaces provide separate 32-bit address/64-bit data buses for the instruction and data sides. The cache controllers are both PLB masters. PLB arbiters are implemented in the FPGA fabric and are available as soft IP cores.
Device Control Register (DCR) Bus Interface
The device control register (DCR) bus has 10 bits of address space for components external to the PPC405 core. Using the DCR bus to manage status and configuration registers reduces PLB traffic and improves system integrity. System resources on the DCR bus are protected or isolated from wayward code since the DCR bus is not part of the system memory map.
Data-Side OCM (DSOCM) * * * * * *
External Interrupt Controller (EIC) Interface
Two level-sensitive user interrupt pins (critical and non-critical) are available. They can be either driven by user defined logic or Xilinx soft interrupt controller IP core outside the Processor Block.
Instruction-Side OCM (ISOCM) The ISOCM interface contains a 64-bit read only port, for instruction fetches, and a 32-bit write only port, to initialize or test the ISBRAM. When implementing the read only port, the user must deassert the write port inputs. The preferred method of initializing the ISBRAM is through the configuration bitstream. * * * * * * 64-bit Data Read Only bus (two instructions per cycle) 32-bit Data Write Only bus (through DCR) Separate 21-bit address to ISBRAM 8-bit DCR Registers: ISCNTL, ISARC 32-bit DCR Registers: ISINIT, ISFILL Two alternatives to write into ISBRAM: BRAM initialization, DCR and write instruction
Clock/Power Management (CPM) Interface
The CPM interface supports several methods of clock distribution and power management. Three modes of operation that reduce power consumption below the normal operational level are available.
Reset Interface
There are three user reset input pins (core, chip, and system) and three user reset output pins for different levels of reset, if required.
Debug Interface
Debugging interfaces on the embedded PPC405 core, consisting of the JTAG and Trace ports, offer access to resources internal to the core and assist in software development. The JTAG port provides basic JTAG chip testing functionality as well as the ability for external debug tools to gain control of the processor for debug purposes. The Trace port furnishes programmers with a mechanism for acquiring instruction execution traces. The JTAG port is compatible with IEEE Std 1149.1, which defines a test access port (TAP) and Boundary-Scan architecture. Extensions to the JTAG interface provide debuggers with processor control that includes stopping, starting, and stepping the PPC405 core. These extensions are compliant with the IEEE 1149.1 specifications for vendor-specific extensions.
Clock/Control Interface Logic
The clock/control interface logic provides proper initialization and connections for PPC405 clock/power management, resets, PLB cycle control, and OCM interfaces. It also couples user signals between the FPGA fabric and the embedded PPC405 CPU core. The processor clock connectivity is similar to CLB clock pins. It can connect either to global clock nets or general routing resources. Therefore the processor clock source can come from DCM, CLB, or user package pin.
CPU-FPGA Interfaces
All Processor Block user pins link up with the general FPGA routing resources through the CPU-FPGA interface. Therefore processor signals have the same routability as other
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DCR Bus
The Trace port provides instruction execution trace information to an external trace tool. The PPC405 core is capable of back trace and forward trace. Back trace is the tracing of instructions prior to a debug event while forward trace is the tracing of instructions after a debug event. The processor JTAG port and the FPGA JTAG port can be accessed independently, or the two can be programmatically linked together and accessed via the dedicated FPGA JTAG pins. For detailed information on the PPC405 JTAG interface, please refer to the "JTAG Interface" section of the PowerPC 405 Processor Block Reference Guide
System Core
System Core
System Core
DCR Bus
Peripheral Core
Peripheral Core
Arbiter
Arbiter
Processor Local Bus
Bus Bridge
On-Chip Peripheral Bus
CoreConnect Bus Architecture Instruction Data
Processor Block
DCR Bus
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Figure 15: CoreConnect Block Diagram * * * Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) Device Control Register (DCR) bus
CoreConnectTM Bus Architecture
The Processor Block is compatible with the CoreConnectTM bus architecture. Any CoreConnect compliant cores including Xilinx soft IP can integrate with the Processor Block through this high-performance bus architecture implemented on FPGA fabric. The CoreConnect architecture provides three buses for interconnecting Processor Blocks, Xilinx soft IP, third party IP, and custom logic, as shown in Figure 15:
High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance. For more information, refer to: http://www-3.ibm.com/chips/techlib/techlib.nfs/productfa milies/CoreConnect_Bus_Architecture/
Functional Description: Embedded PowerPC 405 Core
This section offers a brief overview of the various functional blocks shown in Figure 16.
PLB Master Interface Instruction OCM
MMU
I-Cache Array I-Cache Controller
Fetch & Decode
3-Element Fetch Fetch and Queue Decode (PFB1, Logic PFB0, DCD)
Timers (FIT, PIT, Watchdog)
Instruction Cache Unit
Instruction Shadow TLB (4 Entry)
Cache Units
Data Cache Unit
D-Cache Array D-Cache Controller
Unified TLB (64 Entry)
Timers & Debug
Data Shadow TLB (8 Entry)
Execution Unit (EXU)
32 x 32 GPR ALU MAC
Debug Logic
Execution Unit
PLB Master Interface Data OCM JTAG Instruction Trace
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Figure 16: Embedded PPC405 Core Block Diagram
Embedded PPC405 Core
The embedded PPC405 core is a 32-bit Harvard architecture processor. Figure 16 illustrates its functional blocks:
* * *
Cache units Memory Management unit Fetch Decode unit
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description as controlled by the Data Cache Write-through Register (DCWR) or the Translation Look-aside Buffer (TLB); the cache controller can be tuned for a balance of performance and memory coherency. Write-on-allocate, controlled by the store word on allocate (SWOA) field of the Core Configuration Register 0 (CCR0), can inhibit line fills caused by store misses, to further reduce potential pipeline stalls and unwanted external bus traffic.
* * *
Execution unit Timers Debug logic unit
It operates on instructions in a five stage pipeline consisting of a fetch, decode, execute, write-back, and load write-back stage. Most instructions execute in a single cycle, including loads and stores.
Instruction and Data Cache
The embedded PPC405 core provides an instruction cache unit (ICU) and a data cache unit (DCU) that allow concurrent accesses and minimize pipeline stalls. The instruction and data cache array are 16 KB each. Both cache units are two-way set associative. Each way is organized into 256 lines of 32 bytes (eight words). The instruction set provides a rich assortment of cache control instructions, including instructions to read tag information and data arrays. The PPC405 core accesses external memory through the instruction (ICU) and data cache units (DCU). The cache units each include a 64-bit PLB master interface, cache arrays, and a cache controller. The ICU and DCU handle cache misses as requests over the PLB to another PLB device such as an external bus interface unit. Cache hits are handled as single cycle memory accesses to the instruction and data caches.
Fetch and Decode Logic
The fetch/decode logic maintains a steady flow of instructions to the execution unit by placing up to two instructions in the fetch queue. The fetch queue consists of three buffers: pre-fetch buffer 1 (PFB1), pre-fetch buffer 0 (PFB0), and decode (DCD). The fetch logic ensures that instructions proceed directly to decode when the queue is empty. Static branch prediction as implemented on the PPC405 core takes advantage of some standard statistical properties of code. Branches with negative address displacement are by default assumed taken. Branches that do not test the condition or count registers are also predicted as taken. The PPC405 core bases branch prediction upon these default conditions when a branch is not resolved and speculatively fetches along the predicted path. The default prediction can be overridden by software at assembly or compile time. Branches are examined in the decode and pre-fetch buffer 0 fetch queue stages. Two branch instructions can be handled simultaneously. If the branch in decode is not taken, the fetch logic fetches along the predicted path of the branch instruction in pre-fetch buffer 0. If the branch in decode is taken, the fetch logic ignores the branch instruction in pre-fetch buffer 0.
Instruction Cache Unit (ICU)
The ICU provides one or two instructions per cycle to the instruction queue over a 64-bit bus. A line buffer (built into the output of the array for manufacturing test) enables the ICU to be accessed only once for every four instructions, to reduce power consumption by the array. The ICU can forward any or all of the four or eight words of a line fill to the EXU to minimize pipeline stalls caused by cache misses. The ICU aborts speculative fetches abandoned by the EXU, eliminating unnecessary line fills and enabling the ICU to handle the next EXU fetch. Aborting abandoned requests also eliminates unnecessary external bus activity, thereby increasing external bus utilization.
Execution Unit
The embedded PPC405 core has a single issue execution unit (EXU) containing the register file, arithmetic logic unit (ALU), and the multiply-accumulate (MAC) unit. The execution unit performs all 32-bit PowerPC integer instructions in hardware. The register file is comprised of thirty-two 32-bit general purpose registers (GPR), which are accessed with three read ports and two write ports. During the decode stage, data is read out of the GPRs and fed to the execution unit. Likewise, during the write-back stage, results are written to the GPR. The use of the five ports on the register file enables either a load or a store operation to execute in parallel with an ALU operation.
Data Cache Unit (DCU)
The DCU transfers one, two, three, four, or eight bytes per cycle, depending on the number of byte enables presented by the CPU. The DCU contains a single-element command and store data queue to reduce pipeline stalls; this queue enables the DCU to independently process load/store and cache control instructions. Dynamic PLB request prioritization reduces pipeline stalls even further. When the DCU is busy with a low-priority request while a subsequent storage operation requested by the CPU is stalled; the DCU automatically increases the priority of the current request to the PLB. The DCU provides additional features that allow the programmer to tailor its performance for a given application. The DCU can function in write-back or write-through mode,
Memory Management Unit (MMU)
The embedded PPC405 core has a 4 GB address space, which is presented as a flat address space. The MMU provides address translation, protection functions, and storage attribute control for embedded applications. The MMU supports demand-paged virtual memory and other management schemes that require precise control of logical-to-physical address mapping and flexible
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description The Zone Protection Register (ZPR) enables the system software to override the TLB access controls. For example, the ZPR provides a way to deny read access to application programs. The ZPR can be used to classify storage by type; access by type can be changed without manipulating individual TLB entries. The PowerPC Architecture provides WIU0GE (write-back / write-through, cacheability, user-defined 0, guarded, endian) storage attributes that control memory accesses, using bits in the TLB or, when address translation is disabled, storage attribute control registers. When address translation is enabled, storage attribute control bits in the TLB control the storage attributes associated with the current page. When address translation is disabled, bits in each storage attribute control register control the storage attributes associated with storage regions. Each storage attribute control register contains 32 fields. Each field sets the associated storage attribute for a 128 MB memory region.
memory protection. Working with appropriate system-level software, the MMU provides the following functions: * * * * * * Translation of the 4 GB effective address space into physical addresses Independent enabling of instruction and data translation/protection Page-level access control using the translation mechanism Software control of page replacement strategy Additional control over protection using zones Storage attributes for cache policy and speculative memory access control
The MMU can be disabled under software control. If the MMU is not used, the PPC405 core provides other storage control mechanisms.
Translation Look-Aside Buffer (TLB)
The Translation Look-Aside Buffer (TLB) is the hardware resource that controls translation and protection. It consists of 64 entries, each specifying a page to be translated. The TLB is fully associative; a given page entry can be placed anywhere in the TLB. The translation function of the MMU occurs pre-cache. Cache tags and indexing use physical addresses. Software manages the establishment and replacement of TLB entries. This gives system software significant flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or translation delays, software can reserve several TLB entries in the TLB for globally accessible static mappings. The instruction set provides several instructions used to manage TLB entries. These instructions are privileged and require the software to be executing in supervisor state. Additional TLB instructions are provided to move TLB entry fields to and from GPRs. The MMU divides logical storage into pages. Eight page sizes (1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, and 16 MB) are simultaneously supported, such that, at any given time, the TLB can contain entries for any combination of page sizes. In order for a logical to physical translation to exist, a valid entry for the page containing the logical address must be in the TLB. Addresses for which no TLB entry exists cause TLB-Miss exceptions. To improve performance, four instruction-side and eight data-side TLB entries are kept in shadow arrays. The shadow arrays allow single-cycle address translation and also help to avoid TLB contention between load/store and instruction fetch operations. Hardware manages the replacement and invalidation of shadow-TLB entries; no system software action is required.
Timers
The embedded PPC405 core contains a 64-bit time base and three timers, as shown in Figure 17: * * * Programmable Interval Timer (PIT) Fixed Interval Timer (FIT) Watchdog Timer (WDT)
The time base counter increments either by an internal signal equal to the CPU clock rate or by a separate external timer clock signal. No interrupts are generated when the time base rolls over. The three timers are synchronous with the time base. The PIT is a 32-bit register that decrements at the same rate as the time base is incremented. The user loads the PIT register with a value to create the desired delay. When the register reaches zero, the timer stops decrementing and generates a PIT interrupt. Optionally, the PIT can be programmed to auto-reload the last value written to the PIT register, after which the PIT continues to decrement. The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the selected bit changes from 0 to 1, the PPC405 core generates a FIT interrupt. The WDT provides a periodic critical-class interrupt based on a selected bit in the time base. This interrupt can be used for system error recovery in the event of software or system lockups. Users may select one of four time periods for the interval and the type of reset generated if the WDT expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset unless an exception handler updates the WDT status bit before the timer has completed two of the selected timer intervals.
Memory Protection
When address translation is enabled, the translation mechanism provides a basic level of protection.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description over the CPU core and communicate with a debug tool. The debug tool has read-write access to all registers and can set hardware or software breakpoints. ROM monitors typically use the internal debug mode.
31
Time Base (Incrementer) TBL (32 bits) External Clock Source 0 31 0 TBU (32 bits)
Bit 3 Bit 7
(229 clocks) (225 clocks) WDT Events
Bit 11 (221 clocks) Bit 15 (217 clocks) Bit 11 (221 clocks) Bit 15 (217 clocks) Bit 19 (213 clocks) Bit 23 (2 9 clocks)
FIT Events
In external debug mode, the CPU core enters stop state (stops instruction execution) when a debug event occurs. This mode offers a debug tool read-write access to all registers in the PPC405 core. Once the CPU core is in stop state, the debug tool can start the CPU core, step an instruction, freeze the timers, or set hardware or software break points. In addition to CPU core control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring-up. Communication to a debug tool using external debug mode is through the JTAG port. Debug wait mode offers the same functionality as external debug mode with one exception. In debug wait mode, the CPU core goes into wait state instead of stop state after a debug event. Wait state is identical to stop state until an interrupt occurs. In wait state, the PPC405 core can vector to an exception handler, service an interrupt and return to wait state. This mode is particularly useful when debugging real time control systems. Real-time trace debug mode is always enabled. The debug logic continuously broadcasts instruction trace information to the trace port. When a debug event occurs, the debug logic signals an external debug tool to save instruction trace information before and after the event. The number of instructions traced depends on the trace tool. Debug events signal the debug logic to stop the CPU core, put the CPU core in debug wait state, cause a debug exception or save instruction trace information.
PIT (Decrementer) (32 bits) 0 31
Zero Detect
PIT Events
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Figure 17: Relationship of Timer Facilities to Base Clock
Interrupts
The PPC405 provides an interface to an interrupt controller that is logically outside the PPC405 core. This controller combines the asynchronous interrupt inputs and presents them to the embedded core as a single interrupt signal. The sources of asynchronous interrupts are external signals, the JTAG/debug unit, and any implemented peripherals.
Big Endian and Little Endian Support
The embedded PPC405 core supports big endian or little endian byte ordering for instructions stored in external memory. Since the PowerPC architecture is big endian internally, the ICU rearranges the instructions stored as little endian into the big endian format. Therefore, the instruction cache always contains instructions in big endian format so that the byte ordering is correct for the execution unit. This feature allows the 405 core to be used in systems designed to function in a little endian environment.
Debug Logic
All architected resources on the embedded PPC405 core can be accessed through the debug logic. Upon a debug event, the PPC405 core provides debug information to an external debug tool. Three different types of tools are supported depending on the debug mode: ROM monitors, JTAG debuggers, and instruction trace tools. In internal debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as input and/or output for single-ended I/Os. Two IOBs can be used as a differential pair. A differential pair is always connected to the same switch matrix, as shown in Figure 18. IOB blocks are designed for high-performance I/O, supporting 22 single-ended standards, as well as differential signaling with LVDS, LDT, bus LVDS, and LVPECL.
IOB PAD4 Differential Pair IOB PAD3 Switch Matrix IOB PAD2 Differential Pair IOB PAD1
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Table 10 lists supported I/O standards with Digitally Controlled Impedance. See Digitally Controlled Impedance (DCI), page 31. Table 8: Supported Single-Ended I/O Standards
IOSTANDARD Attribute LVTTL (1) LVCMOS33 (1) LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III _18 HSTL_IV_18 SSTL2_I SSTL2_II SSTL18_I (4) SSTL18_II Output VCCO 3.3 3.3 2.5 1.8 1.5
Note (2) Note (2) Note (2) Note (3) Note (3)
Input VCCO 3.3 3.3 2.5 1.8 1.5
Note (2) Note (2) Note (2) Note (3) Note (3)
Input VREF N/R N/R N/R N/R N/R N/R N/R N/R 0.8 1.0 0.75 0.75 0.9 0.9 0.9 0.9 1.1 1.1 1.25 1.25 0.9 0.9
Board Termination Voltage (VTT) N/R N/R N/R N/R N/R N/R N/R N/R 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.25 1.25 0.9 0.9
1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5 1.8 1.8
N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R
Figure 18: Virtex-II Pro Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectIO-Ultra inputs and outputs that support a wide variety of I/O signaling standards. In addition to the internal supply voltage (VCCINT = 1.5V), output driver supply voltage (VCCO) is dependent on the I/O standard (see Table 8 and Table 9). An auxiliary supply voltage (VCCAUX = 2.5V) is required, regardless of the I/O standard used. For exact supply voltage absolute maximum ratings, see Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. All of the user IOBs have fixed-clamp diodes to VCCO and to ground. The IOBs are not compatible or compliant with 5V I/O standards (not 5V-tolerant).
Notes: 1. Refer to XAPP659 for more details on interfacing to these 3.3V standards. 2. For PCI and PCI-X standards, refer to XAPP653. 3. VCCO of GTL or GTLP should not be lower than the termination voltage or the voltage seen at the I/O pad. Example: If the pin High level is 1.5V, connect VCCO to 1.5V. 4. SSTL18_I is not a JEDEC-supported standard. 5. N/R = no requirement.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Table 10: Supported DCI I/O Standards (Continued)
I/O Standard
LVDS_25_DCI LVDSEXT_25_DCI
Table 9: Supported Differential Signal I/O Standards
I/O Standard
LDT_25 LVDS_25 LVDSEXT_25 BLVDS_25 ULVDS_25 LVPECL_25 LDT_25_DT (1) LVDS_25_DT (1) LVDSEXT_25_DT (1) ULVDS_25_DT (1)
Output VCCO
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
Input VCCO
N/R N/R N/R N/R N/R N/R 2.5 2.5 2.5 2.5
Input VREF
N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R
Output VOD
0.500 - 0.740 0.247 - 0.454 0.440 - 0.820 0.250 - 0.450 0.500 - 0.740 0.345 - 1.185 0.500 - 0.740 0.247 - 0.454 0.330 - 0.700 0.500 - 0.740
Output VCCO
2.5 2.5
Input VCCO
2.5 2.5
Input VREF
N/R N/R
Termination Type
Split Split
Notes: 1. LVDCI_XX is LVCMOS output controlled impedance buffers, matching all or half of the reference resistors. 2. These are SSTL compatible. 3. SSTL18_I is not a JEDEC-supported standard. 4. N/R = no requirement.
Logic Resources
IOB blocks include six storage elements, as shown in Figure 19.
IOB DDR mux Reg OCK1 Input
Notes: 1. These standards support on-chip 100 termination. 2. N/R = no requirement.
Table 10: Supported DCI I/O Standards
I/O Standard
LVDCI_33 (1) LVDCI_25 LVDCI_DV2_25 LVDCI_18 LVDCI_DV2_18 LVDCI_15 LVDCI_DV2_15 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL2_I_DCI (2) SSTL2_II_DCI (2) SSTL18_I_DCI (3) SSTL18_II_DCI
Reg ICK1
Output VCCO
3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5 1.8 1.8
Input VCCO
3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5 1.8 1.8
Input VREF
N/R N/R N/R N/R N/R N/R N/R 0.8 1.0 0.75 0.75 0.9 0.9 0.9 0.9 1.1 1.1 1.25 1.25 0.9 0.9
Termination Type
Series Series Series Series Series Series Series Single Single Split Split Single Single Split Split Single Single Split Split Split Split
Reg OCK2 3-State Reg ICK2 DDR mux Reg OCK1 PAD Reg OCK2 Output
DS031_29_100900
Figure 19: Virtex-II Pro IOB Block Each storage element can be configured either as an edge-triggered D-type flip-flop or as a level-sensitive latch. On the input, output, and 3-state path, one or two DDR registers can be used. Double data rate is directly accomplished by the two registers on each path, clocked by the rising edges (or falling edges) from two different clock nets. The two clock signals are generated by the DCM and must be 180 degrees out of phase, as shown in Figure 20. There are two input, output, and 3-state data signals, each being alternately clocked out.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DCM 0 FDDR D1 Q1 CLK1
DCM 180 0 FDDR D1 Q1 CLK1
DDR MUX
Q
DDR MUX
Q
D2 Q2 CLK2
D2 Q2 CLK2
DS083-2_26_122001
Figure 20: Double Data Rate Registers This DDR mechanism can be used to mirror a copy of the clock on the output. This is useful for propagating a clock along the data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load. Virtex-II Pro devices can produce many copies of a clock with very little skew. Each group of two registers has a clock enable signal (ICE for the input registers, OCE for the output registers, and TCE for the 3-state registers). The clock enable signals are active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. Each IOB block has common synchronous or asynchronous set and reset (SR and REV signals). Two neighboring IOBs have a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. If two adjacent IOBs using DDR registers do not share the same clock signals on their clock pins (ICLK1, ICLK2, OTCLK1, and OTCLK2), one of the clock signals will be unroutable. The IOB pairing is identical to the LVDS IOB pairs. Hence, the package pin-out table can also be used for pin assignment to avoid conflict. SR forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic 1. SRLOW forces a logic "0". When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition. The initial state after configuration or global initialization state is defined by a separate INIT0 and INIT1 attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1. For each storage element, the SRHIGH, SRLOW, INIT0, and INIT1 attributes are independent. Synchronous or asynchronous set / reset is consistent in an IOB block. All the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed. Each register or latch, independent of all other registers or latches, can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear)
The synchronous reset overrides a set, and an asynchronous clear overrides a preset. Refer to Figure 21.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
(O/T) 1 Attribute INIT1 INIT0 SRHIGH SRLOW
FF LATCH (O/T) CE (O/T) CLK1 SR Shared by all registers REV FF LATCH D2 Q2 D1 Q1
CE CK1 SR REV FF1 DDR MUX FF2 (OQ or TQ)
(O/T) CLK2
CE CK2 SR REV
Attribute INIT1 INIT0 SRHIGH SRLOW
(O/T) 2
Reset Type SYNC ASYNC
DS031_25_110300
Figure 21: Register / Latch Configuration in an IOB Block
Input/Output Individual Options
VCCO OBUF Clamp Diode VCCO Program Current
40K - 120K
Weak Keeper
Each device pad has optional pull-up/pull-down resistors and weak-keeper circuit in the LVTTL, LVCMOS, and PCI SelectIO-Ultra configurations, as illustrated in Figure 22. Values of the optional pull-up and pull-down resistors fall within a range of 40 K to 120 K when VCCO = 2.5V (from 2.38V to 2.63V only). The clamp diodes are always present, even when power is not. The optional weak-keeper circuit is connected to each user I/O pad. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low. If the pin is connected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. An enabled pull-up or pull-down overrides the weak-keeper circuit. LVCMOS25 sinks and sources current up to 24 mA. The current is programmable (see Table 11). Drive strength and slew rate controls for each output driver minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew rate controls are not available.
PAD VCCO
40K - 120K
Program Delay IBUF
VCCAUX = 2.5V VCCINT = 1.5V
DS083-2_07_101801
Figure 22: LVTTL, LVCMOS, or PCI SelectIO-Ultra Standard
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 11: LVCMOS Programmable Currents (Sink and Source) SelectIO-Ultra LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 2 mA 2 mA 2 mA 2 mA 2 mA Programmable Current (Worst-Case Guaranteed Minimum) 4 mA 4 mA 4 mA 4 mA 4 mA 6 mA 6 mA 6 mA 6 mA 6 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 16 mA 16 mA 16 mA 16 mA 16 mA 24 mA 24 mA 24 mA n/a n/a
Figure 23 shows the SSTL2, SSTL18, and HSTL configurations. HSTL can sink current up to 48 mA. (HSTL IV)
VCCO OBUF Clamp Diode
Input Path
The Virtex-II Pro IOB input path routes input signals directly to internal logic and / or through an optional input flip-flop or latch, or through the DDR input registers. An optional delay element at the D-input of the storage element eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the Virtex-II Pro device, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in the same bank. See I/O banking description.
PAD
Output Path
VREF VCCAUX = 2.5V VCCINT = 1.5V
DS031_24_100900
Figure 23: SSTL or HSTL SelectIO-Ultra Standards All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Virtex-II Pro uses two memory cells to control the configuration of an I/O as an input. This is to reduce the probability of an I/O configured as an input from flipping to an output when subjected to a single event upset (SEU) in space applications. Prior to configuration, all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive. The dedicated pin HSWAP_EN controls the pull-up resistors prior to configuration. By default, HSWAP_EN is set High, which disables the pull-up resistors on user I/O pins. When HSWAP_EN is set Low, the pull-up resistors are activated on user I/O pins. All Virtex-II Pro IOBs (except RocketIO transceiver pins) support IEEE 1149.1 and IEEE 1532 compatible Boundary-Scan testing.
The output path includes a 3-state output buffer that drives the output signal onto the pad. The output and / or the 3-state signal can be routed to the buffer directly from the internal logic or through an output / 3-state flip-flop or latch, or through the DDR output / 3-state registers. Each output driver can be individually programmed for a wide range of low-voltage signaling standards. In most signaling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in the same bank. See I/O banking description.
I/O Banking
Some of the I/O standards described above require VCCO and VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOB blocks, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from dividing each edge of the FPGA into two banks, as shown in Figure 24 and Figure 25. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description nect within the package. These unconnected pins can be left unconnected externally, or, if necessary, they can be connected to VCCO to permit migration to a larger device.
Bank 0 Bank 7 Bank 1 Bank 2
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different input, output, and bi-directional standards in the same bank: 1. Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank.
Compatible example: SSTL2_I and LVDS_25 outputs Incompatible example: SSTL2_I (output VCCO = 2.5V) and LVCMOS33 (output VCCO = 3.3V) outputs
Bank 6
Bank 5
Bank 4
ug002_c2_014_041403
Figure 24: I/O Banks: Wire-Bond Packages (FG) Top View
Bank 3
2. Combining input standards only. Input standards with the same input VCCO and input VREF requirements can be combined in the same bank.
Compatible example: LVCMOS15 and HSTL_IV inputs Incompatible example: LVCMOS15 (input VCCO = 1.5V) and LVCMOS18 (input VCCO = 1.8V) inputs Incompatible example: HSTL_I_DCI_18 (VREF = 0.9V) and HSTL_IV_DCI_18 (VREF = 1.1V) inputs
Bank 1 Bank 2
Bank 0 Bank 7 Bank 6
Bank 3
Bank 4
Bank 5
3. Combining input standards and output standards. Input standards and output standards with the same input VCCO and output VCCO requirement can be combined in the same bank.
Compatible example: LVDS_25 output and HSTL_I input Incompatible example: LVDS_25 output (output VCCO = 2.5V) and HSTL_I_DCI_18 input (input VCCO = 1.8V)
ds031_66_041403
Figure 25: I/O Banks: Flip-Chip Packages (FF) Top View Some input standards require a user-supplied threshold voltage (VREF), and certain user-I/O pins are automatically configured as VREF inputs. Approximately one in six of the I/O pins in the bank assume this role. VREF pins within a bank are interconnected internally, thus only one VREF voltage can be used within each bank. However, for correct operation, all VREF pins in the bank must be connected to the external reference voltage source. The VCCO and the VREF pins for each bank appear in the device pinout tables. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All VREF pins for the largest device anticipated must be connected to the VREF voltage and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not conDS083 (v4.7) November 5, 2007 Product Specification
4. Combining bi-directional standards with input or output standards. When combining bi-directional I/O with other standards, make sure the bi-directional standard can meet rules 1 through 3 above. 5. Additional rules for combining DCI I/O standards. a. No more than one Single Termination type (input or output) is allowed in the same bank.
Incompatible example: HSTL_IV_DCI input and HSTL_III_DCI input
b.
No more than one Split Termination type (input or output) is allowed in the same bank.
Incompatible example: HSTL_I_DCI input and HSTL_II_DCI input
The implementation tools will enforce the above design rules. Table 12, page 30, summarizes all standards and voltage supplies.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Table 12: Summary of Voltage Supply Requirements for All Input and Output Standards (Continued)
VCCO I/O Standard HSTL_III_18 HSTL_IV_18 HSTL_I_18
Note (3)
Table 12: Summary of Voltage Supply Requirements for All Input and Output Standards
VCCO I/O Standard LVTTL (1) LVCMOS33 (1) LVDCI_33 (1) PCIX (2) PCI33_3 (2) PCI66_3 (2) LVDS_25 LVDSEXT_25 LDT_25 ULVDS_25
Note (3)
VREF Input N/R N/R N/R
Termination Type Output N/R N/R Series N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R Series Series N/R N/R N/R Split N/R N/R N/R N/R Input N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R N/R Split Split Split Split N/R N/R N/R N/R
VREF Input 1.1 1.1 0.9 0.9 0.9 0.9 N/R
Termination Type Output N/R N/R N/R N/R N/R N/R N/R Series Series N/R Single N/R Split N/R Split N/R N/R N/R N/R N/R Series Series Single N/R Single N/R Split Single N/R N/R Input N/R N/R N/R N/R N/R N/R N/R N/R N/R Single Single Split Split Split Split N/R N/R N/R N/R N/R N/R N/R Single Single Single Split Split Single N/R N/R
Output
Input
Output
Input
3.3
3.3 N/R N/R N/R N/R N/R N/R N/R N/R N/R 1.25 1.25 N/R
HSTL_II_18 SSTL18_I SSTL18_II LVCMOS18 LVDCI_18 LVDCI_DV2_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 HSTL_I_DCI_18 HSTL_II_DCI_18 SSTL18_I_DCI SSTL18_II_DCI HSTL_III HSTL_IV
Note (3)
1.8
N/R N/R 1.1 1.8 1.1 0.9 0.9 0.9 0.9 0.9 0.9 0.75 0.75 N/R N/R
BLVDS_25 LVPECL_25 SSTL2_I SSTL2_II LVCMOS25 LVDCI_25 LVDCI_DV2_25 LVDS_25_DCI LVDSEXT_25_DCI SSTL2_I_DCI SSTL2_II_DCI LVDS_25_DT LVDSEXT_25_DT LDT_25_DT ULVDS_25_DT 2.5 2.5
N/R N/R N/R N/R 1.25 1.25 N/R N/R N/R N/R
HSTL_I HSTL_II LVCMOS15 LVDCI_15 1.5 LVDCI_DV2_15 GTLP_DCI 1.5 HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI HSTL_II_DCI GTL_DCI GTLP N/R GTL
Note (3)
N/R 1 0.9 0.9 0.75 0.75 1.2 1.2 0.8 1 0.8
Notes: 1. See application note XAPP659 for more detailed information. 2. See application note XAPP653 for more detailed information. 3. Pin voltage must not exceed VCCO. 4. N/R = no requirement.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Controlled Impedance Drivers (Series Termination) DCI can be used to provide a buffer with a controlled output impedance. It is desirable for this output impedance to match the transmission line impedance (Z0). Virtex-II Pro input buffers also support LVDCI and LVDCI_DV2.
IOB Z Z0
Digitally Controlled Impedance (DCI)
Today's chip output signals with fast edge rates require termination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Virtex-II Pro XCITE DCI provides controlled impedance drivers and on-chip termination for single-ended and differential I/Os. This eliminates the need for external resistors and improves signal integrity. The DCI feature can be used on any IOB by selecting one of the DCI I/O standards. When applied to inputs, DCI provides input parallel termination. When applied to outputs, DCI provides controlled impedance drivers (series termination) or output parallel termination. DCI operates independently on each I/O bank. When a DCI I/O standard is used in a particular I/O bank, external reference resistors must be connected to two dual-function pins on the bank. These resistors, voltage reference of N transistor (VRN) and the voltage reference of P transistor (VRP) are shown in Figure 26.
1 Bank DCI DCI
Virtex-II Pro DCI VCCO = 3.3V, 2.5 V, 1.8 V, or 1.5 V
DS083-2_09_082902
Figure 27: Internal Series Termination Table 13: SelectIO-Ultra Controlled Impedance Buffers
VCCO 3.3V 2.5V 1.8V 1.5V DCI LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 DCI Half Impedance N/A LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15
Controlled Impedance Terminations (Parallel) DCI also provides on-chip termination for SSTL2, SSTL18, HSTL (Class I, II, III, or IV), LVDS_25, LVDSEXT_25, and GTL/GTLP receivers or transmitters on bidirectional lines. Table 14 and Table 15 list the on-chip parallel terminations available in Virtex-II Pro devices. VCCO must be set according to Table 10. There is a VCCO requirement for GTL_DCI and GTLP_DCI, due to the on-chip termination resistor.
VCCO RREF (1%) VRN VRP RREF (1%) GND
DS031_50_101200
DCI DCI
Table 14: SelectIO-Ultra Buffers With On-Chip Parallel Termination
IOSTANDARD Attribute I/O Standard Description SSTL Class I, 2.5V SSTL Class II, 2.5V SSTL Class I, 1.8V SSTL Class II, 1.8V HSTL Class I HSTL Class I, 1.8V HSTL Class II HSTL Class II, 1.8V HSTL Class III HSTL Class III, 1.8V HSTL Class IV HSTL Class IV, 1.8V GTL GTL Plus
Notes: 1. SSTL compatible.
External Termination SSTL2_I SSTL2_II SSTL18_I SSTL18_II HSTL_I HSTL_I_18 HSTL_II HSTL_II_18 HSTL_III HSTL_III_18 HSTL_IV HSTL_IV_18 GTL GTLP
On-Chip Termination SSTL2_I_DCI (1) SSTL2_II_DCI (1) SSTL18_I_DCI SSTL18_II_DCI HSTL_I_DCI HSTL_I_DCI_18 HSTL_II_DCI HSTL_II_DCI_18 HSTL_III_DCI HSTL_III_DCI_18 HSTL_IV_DCI HSTL_IV_DCI_18 GTL_DCI GTLP_DCI
Figure 26: DCI in a Virtex-II Pro Bank When used with a terminated I/O standard, the value of the resistors are specified by the standard (typically 50). When used with a controlled impedance driver, the resistors set the output impedance of the driver within the specified range (20 to 100). For all series and parallel terminations listed in Table 13 and Table 14, the reference resistors must have the same value for any given bank. One percent resistors are recommended. The DCI system adjusts the I/O impedance to match the two external reference resistors, or half of the reference resistors, and compensates for impedance changes due to voltage and/or temperature fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 15: SelectIO-Ultra Differential Buffers With On-Chip Termination
IOSTANDARD Attribute I/O Standard Description LVDS 2.5V LVDS Extended 2.5V External Termination LVDS_25 LVDSEXT_25 On-Chip Termination LVDS_25_DCI LVDSEXT_25_DCI
Figure 28 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the Virtex-II Pro Platform FPGA User Guide.
HSTL_I HSTL_II HSTL_III HSTL_IV
VCCO/2
VCCO/2 R Z0
VCCO/2 R Z0
VCCO R
VCCO R Z0
VCCO R
Conventional
R Z0
VCCO/2
VCCO 2R Z0 2R Virtex-II Pro DCI
VCCO/2 R Z0 Virtex-II Pro DCI
DCI Transmit Conventional Receive
Virtex-II Pro DCI
VCCO R
VCCO R Z0 Virtex-II Pro DCI
VCCO R
R Z0
VCCO
VCCO/2 R Z0
VCCO 2R Z0 Virtex-II Pro DCI VCCO R 2R Virtex-II Pro DCI VCCO R Z0 Virtex-II Pro DCI VCCO R
Conventional Transmit DCI Receive
2R Z0 2R Virtex-II Pro DCI
VCCO 2R
VCCO 2R Z0 2R Virtex-II Pro DCI
VCCO 2R Z0 Virtex-II Pro DCI Virtex-II Pro DCI VCCO R 2R Virtex-II Pro DCI VCCO R Z0 Virtex-II Pro DCI VCCO R
DCI Transmit DCI Receive
Z0 2R Virtex-II Pro DCI
VCCO 2R Z0
VCCO 2R 2R Virtex-II Pro DCI
VCCO R
VCCO R Z0
Bidirectional
N/A
2R Virtex-II Pro DCI
N/A
Virtex-II Pro DCI
Virtex-II Pro DCI
Reference Resistor
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
DS083-2_65a_082102
Recommended Z0
Figure 28: HSTL DCI Usage Examples
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Figure 29 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL18_I_DCI, and SSTL18_II_DCI I/O standards. For a complete list, see the Virtex-II Pro Platform FPGA User Guide.
SSTL2_I or SSTL18_I
VCCO/2 R VCCO/2 R VCCO/2 R Z0
SSTL2_II or SSTL18_II
Conventional
R/2
Z0 R/2
VCCO/2
VCCO 25(1) 2R Z0 2R
VCCO/2 R
DCI Transmit Conventional Receive
25(1) Z0 Virtex-II Pro DCI
R
Virtex-II Pro DCI
VCCO
VCCO/2 R Z0 R/2
VCCO 2R
Conventional Transmit DCI Receive
2R Z0 R/2 2R Virtex-II Pro DCI
2R Virtex-II Pro DCI
25(1)
VCCO 2R Z0 25(1)
VCCO 2R Z0 2R Virtex-II Pro DCI
VCCO 2R
DCI Transmit DCI Receive
Virtex-II Pro DCI
2R Virtex-II Pro DCI
2R Virtex-II Pro DCI
VCCO 25(1) 2R Z0
VCCO 2R 2R 25 Virtex-II Pro DCI
Bidirectional
N/A
2R Virtex-II Pro DCI
Reference Resistor
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
DS083-2_65b_011603
Recommended Z0(2)
Notes: 1. The SSTL-compatible 25 series resistor is accounted for in the DCI buffer, and it is not DCI controlled. 2. Z0 is the recommended PCB trace impedance.
Figure 29: SSTL DCI Usage Examples
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description The on-chip input differential termination in Virtex-II Pro provides major advantages over the external resistor or the DCI termination solution: * * * * Eliminates the stub at the receiver completely and therefore greatly improve signal integrity Consumes less power than DCI termination Supports LDT (not supported by DCI termination) Frees up VRP/VRN pins
Figure 30 provides examples illustrating the use of the LVDS_25_DCI and LVDSEXT_25_DCI I/O standards. For a complete list, see the Virtex-II Pro Platform FPGA User Guide.
LVDS_25_DCI and LVDSEXT_25_DCI Receiver
Z0
Conventional
2R
Figure 31 provides examples illustrating the use of the LVDS_25_DT, LVDSEXT_25_DT, LDT_25_DT, and ULVDS_25_DT I/O standards. For further details, refer to Solution Record 17244. Also see the Virtex-II Pro Platform FPGA User Guide for more design information.
LVDS_25_DT, LVDSEXT_25_DT, LDT_25_DT, and ULVDS_25_DT Receiver Virtex-II Pro LVDS
Z0
Z0
VCCO 2R
Z0
Conventional
2R
2R Conventional Transmit DCI Receive
Z0 Z0
VCCO 2R 2R Virtex-II Pro LVDS DCI Virtex-II Pro LVDS
Reference Resistor Recommended Z0
VRN = VRP = R = Z0 50
NOTE: Only LVDS25_DCI is supported (VCCO = 2.5V only)
DS083-2_65c_022103
Z0
Conventional Transmit, On-Chip Differential Termination Receive
100
Figure 30: LVDS DCI Usage Examples
Z0
On-Chip Differential Termination
Virtex-II Pro provides a true 100 differential termination (DT) across the input differential receiver terminals. The LVDS_25_DT, LVDSEXT_25_DT, LDT_25_DT, and ULVDS_25_DT standards support on-chip differential termination.
Recommended Z0 50
Virtex-II Pro LVDS On-Chip Differential Termination
NOTE: Only 2.5V LVDS standards are supported (VCCO = 2.5V only)
DS083-2_65e_052703
Figure 31: LVDS Differential Termination Usage Examples
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Configurable Logic Blocks (CLBs)
The Virtex-II Pro configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing matrix, as shown in Figure 32. A CLB element comprises 4 similar slices, with fast local feedback within the CLB. The four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain.
COUT TBUF TBUF Slice X1Y1 Slice X1Y0 SHIFT Slice X0Y1 Slice X0Y0 CIN CIN
Configurations
Look-Up Table Virtex-II Pro function generators are implemented as 4-input look-up tables (LUTs). Four independent inputs are provided to each of the two function generators in a slice (F and G). These function generators are each capable of implementing any arbitrarily defined boolean function of four inputs. The propagation delay is therefore independent of the function implemented. Signals from the function generators can exit the slice (X or Y output), can input the XOR dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the D input of the storage element, or go to the MUXF5 (not shown in Figure 34). In addition to the basic LUTs, the Virtex-II Pro slice contains logic (MUXF5 and MUXFX multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. The MUXFX is either MUXF6, MUXF7, or MUXF8 according to the slice considered in the CLB. Selected functions up to nine inputs (MUXF5 multiplexer) can be implemented in one slice. The MUXFX can also be a MUXF6, MUXF7, or MUXF8 multiplexer to map any function of six, seven, or eight inputs and selected wide logic functions. Register/Latch The storage elements in a Virtex-II Pro slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D input can be directly driven by the X or Y output via the DX or DY input, or by the slice inputs bypassing the function generators via the BX or BY input. The clock enable signal (CE) is active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR and BY slice inputs). SR forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic 1 when SR is asserted. SRLOW forces a logic 0. When SR is used, an optional second input (BY) forces the storage element into the opposite state via the REV pin. The reset condition is predominant over the set condition. (See Figure 35.) The initial state after configuration or global initial state is defined by a separate INIT0 and INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. For each slice, set and reset can be set to be synchronous or asynchronous. Virtex-II Pro devices also have the ability to set INIT0 and INIT1 independent of SRHIGH and SRLOW. The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage elements in one slice. All of the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed.
Switch Matrix
COUT
Fast Connects to neighbors
DS083-2_32_122001
Figure 32: Virtex-II Pro CLB Element
Slice Description
Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. As shown in Figure 33, each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM+ memory, or a 16-bit variable-tap shift register element. The output from the function generator in each slice drives both the slice output and the D input of the storage element. Figure 34 shows a more detailed view of a single slice.
RAM16
ORCY MUXFx
SRL16 LUT G RAM16 MUXF5 SRL16 LUT F CY Register/ Latch CY Register/ Latch
Arithmetic Logic
DS083-2_31_122001
Figure 33: Virtex-II Pro Slice Configuration
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
SHIFTIN
COUT
SOPIN 0 Dual-Port Shift-Reg G4 G3 G2 G1 WG4 WG3 WG2 WG1 ALTDIG MULTAND 1 0 BY SLICEWE[2:0] G2 PROD G1 CYOG BY A4 LUT A3 RAM A2 ROM A1 D WG4 G WG3 WG2 MC15 WG1 DI WS
ORCY SOPOUT
YBMUX 1 MUXCY 1 0
YB
GYMUX
Y DY
XORG FF LATCH DYMUX CE CLK D Q
Q
Y CE CK SR REV
WSG WE[2:0] WE CLK WSF
SHIFTOUT
SR DIG MUXCY 1 0
CE CLK SR CIN
DS031_01_112502
Shared between x & y Registers
Figure 34: Virtex-II Pro Slice (Top Half)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description * * * *
YQ Attribute INIT1 INIT0 SRHIGH SRLOW
FFY FF LATCH DY D Q
Single-Port 128 x 1-bit RAM Dual-Port 16 x 4-bit RAM Dual-Port 32 x 2-bit RAM Dual-Port 64 x 1-bit RAM
CE CK SR REV BY FFX FF LATCH DX CE CLK SR BX D CE CK SR REV Q
Distributed SelectRAM+ memory modules are synchronous (write) resources. The combinatorial read access time is extremely fast, while the synchronous write simplifies high-speed designs. A synchronous read can be implemented with a storage element in the same slice. The distributed SelectRAM+ memory and the storage element share the same clock input. A Write Enable (WE) input is active High, and is driven by the SR input. Table 16 shows the number of LUTs (2 per slice) occupied by each distributed SelectRAM+ configuration. Table 16: Distributed SelectRAM+ Configurations RAM 16 x 1S 16 x 1D 32 x 1S 32 x 1D 64 x 1S 64 x 1D 128 x 1S Number of LUTs 1 2 2 4 4 8 8
XQ Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC
DS083-2_22_122001
Figure 35: Register / Latch Configuration in a Slice The set and reset functionality of a register or a latch can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear)
Notes: 1. S = single-port configuration; D = dual-port configuration
For single-port configurations, distributed SelectRAM+ memory has one address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed SelectRAM+ memory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. The function generator (LUT) has separated read address inputs (A1, A2, A3, A4) and write address inputs (WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4). In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator (R/W port) is connected with shared read and write addresses. The second function generator has the A inputs (read) connected to the second read-only port address and the W inputs (write) shared with the first read/write port
The synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. Distributed SelectRAM+ Memory Each function generator (LUT) can implement a 16 x 1-bit synchronous RAM resource called a distributed SelectRAM+ element. SelectRAM+ elements are configurable within a CLB to implement the following: * * * Single-Port 16 x 8-bit RAM Single-Port 32 x 4-bit RAM Single-Port 64 x 2-bit RAM
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Figure 36, Figure 37, and Figure 38 illustrate various example configurations.
RAM 16x1S DPRA[3:0] A[3:0] 4 4 (BY) WSG (SR) WE CK (optional) RAM A[4:1] WG[4:1] WS D DI A[3:0] D D Q Output Registered Output D (BY) 4 4
RAM 16x1D
dual_port RAM G[4:1] D WG[4:1] WS DI
DPO
WSG WE CK
WE WCLK
DS031_02_100900
Figure 36: Distributed SelectRAM+ (RAM16x1S)
A[3:0]
4
dual_port RAM G[4:1] D WG[4:1] WS DI
SPO
RAM 32x1S A[4] A[3:0] (BX) 4 RAM G[4:1] WG[4:1] WS D (BY) WSG WE0 WE CK WSF WS DI RAM D F[4:1] WF[4:1]
DS031_04_110100
WSG
D
WE WCLK
(SR)
WE CK
DI
WE WCLK
(SR)
Output F5MUX D Q Registered Output
Figure 38: Dual-Port Distributed SelectRAM+ (RAM16x1D) Similar to the RAM configuration, each function generator (LUT) can implement a 16 x 1-bit ROM. Five configurations are available: ROM16x1, ROM32x1, ROM64x1, ROM128x1, and ROM256x1. The ROM elements are cascadable to implement wider or/and deeper ROM. ROM contents are loaded at configuration. Table 17 shows the number of LUTs occupied by each configuration. Table 17: ROM Configuration ROM 16 x 1 32 x 1 64 x 1 128 x 1 256 x 1 Number of LUTs 1 2 4 8 (1 CLB) 16 (2 CLBs)
4
(optional)
DS083-2_10_050901
Figure 37: Single-Port Distributed SelectRAM+ (RAM32x1S)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Shift Registers Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 39. A dynamic read access is performed through the 4-bit address bus, A[3:0]. The configurable 16-bit shift register cannot be set or reset. The read is asynchronous; however, the storage element or flip-flop is available to implement a synchronous read. Any of the 16 bits can be read out asynchronously by varying the address. The storage element should always be used with a constant address. For example, when building an 8-bit shift register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip-flop. The overall system performance is improved by using the superior clock-to-out of the flip-flops.
SHIFTIN SRLC16 1 Shift Chain in CLB IN
DI D SRLC16 MC15
FF
DI D SRLC16 MC15 SLICE S3
FF
SHIFTOUT
SHIFTIN DI D SRLC16 MC15 FF
SHIFT-REG A[3:0] 4 A[4:1] D MC15 D WS D(BY) WSG CE (SR) CLK WE CK (optional) SHIFTIN DI D SRLC16 MC15 SHIFTOUT
DS031_05_110600
Output Q Registered Output SLICE S2
DI D SRLC16 MC15
FF
DI
SHIFTOUT
FF
Figure 39: Shift Register Configurations An additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary LUT output. (See Figure 40.) Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the MUXF5, MUXF6, and MUXF7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one CLB.
DI D SRLC16 MC15
FF SLICE S1 SHIFTOUT
SHIFTIN DI D SRLC16 MC15 FF
DI D SRLC16 MC15
FF SLICE S0 OUT CASCADABLE OUT
DS031_06_110200
CLB
Figure 40: Cascadable Shift Register
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Each Virtex-II Pro slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 41. Each CLB element has two MUXF6 multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. Examples of multiplexers are shown in the Virtex-II Pro Platform FPGA User Guide. Any LUT can implement a 2:1 multiplexer.
Multiplexers Virtex-II Pro function generators and associated multiplexers can implement the following: * * * * 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one CLB element (4 slices) 32:1 multiplexer in two CLB elements (8 slices)
F8
Slice S3
G F F5
MUXF8 combines the two MUXF7 outputs (Two CLBs)
F6
F
F7
F5
Slice S2
G
MUXF6 combines the two MUXF5 outputs from slices S2 and S3
G F F5
Slice S1
MUXF7 combines the two MUXF6 outputs from slices S0 and S2
F6
G F F5
Slice S0
MUXF6 combines the two MUXF6 outputs from slices S0 and S1
CLB
DS031_08_110200
Figure 41: MUXF5 and MUXFX multiplexers Fast Lookahead Carry Logic Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II Pro CLB has two separate carry chains, as shown in the Figure 42. The height of the carry chains is two bits per slice. The carry chain in the Virtex-II Pro device is running upward. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. Arithmetic Logic The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, a dedicated AND (MULT_AND) gate (shown in Figure 34) improves the efficiency of multiplier implementation.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
COUT to S0 of the next CLB
COUT to CIN of S2 of the next CLB
OI LUT (First Carry Chain)
MUXCY FF
SLICE S3 OI LUT MUXCY FF
CIN COUT OI LUT MUXCY FF
SLICE S2 OI OI LUT MUXCY FF LUT MUXCY FF
OI LUT
MUXCY FF
SLICE S1
CIN COUT OI LUT MUXCY FF
(Second Carry Chain)
OI LUT
MUXCY FF
SLICE S0
CIN
CIN
CLB
DS031_07_110200
Figure 42: Fast Carry Logic Path
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description implementing large, flexible SOP chains. One input of each ORCY is connected through the fast SOP chain to the output of the previous ORCY in the same slice row. The second input is connected to the output of the top MUXCY in the same slice, as shown in Figure 43.
Sum of Products Each Virtex-II Pro slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are designed for
ORCY 4 4
ORCY 4
ORCY 4
ORCY SOP
LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
Slice 1 4 LUT
MUXCY
Slice 3 4 LUT
MUXCY
Slice 1 4 LUT
MUXCY
Slice 3 4 LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
4
LUT
MUXCY
Slice 0 4 LUT
MUXCY
Slice 2 4 LUT
MUXCY
Slice 0 4 LUT
MUXCY
Slice 2 4 LUT
MUXCY
VCC
VCC CLB
VCC
VCC CLB
ds031_64_110300
Figure 43: Horizontal Cascade Chain LUTs and MUXCYs can implement large AND gates or other combinatorial logic functions. Figure 44 illustrates LUT and MUXCY resources configured as a 16-input AND gate.
OUT
4 0 LUT
MUXCY 1 Slice
"0" 4 LUT 0 "0"
MUXCY 1
16
AND
OUT
4 0 LUT
MUXCY 1
"0" 4 LUT 0 MUXCY 1
Slice
VCC
DS031_41_110600
Figure 44: Wide-Input AND Gate (16 Inputs)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Locations / Organization Four horizontal routing resources per CLB are provided for on-chip 3-state buses. Each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in Figure 46. The switch matrices corresponding to SelectRAM+ memory and multiplier or I/O blocks are skipped. Number of 3-State Buffers Table 18 shows the number of 3-state buffers available in each Virtex-II Pro device. The number of 3-state buffers is twice the number of CLB elements. Table 18: Virtex-II Pro 3-State Buffers
Slice S3 Slice S2 Slice S1 Slice S0
DS031_37_060700
3-State Buffers
Introduction Each Virtex-II Pro CLB contains two 3-state drivers (TBUFs) that can drive on-chip buses. Each 3-state buffer has its own 3-state control pin and its own input pin. Each of the four slices have access to the two 3-state buffers through the switch matrix, as shown in Figure 45. TBUFs in neighboring CLBs can access slice outputs by direct connects. The outputs of the 3-state buffers drive horizontal routing resources used to implement 3-state buses.
TBUF
TBUF
Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
3-State Buffers per Row 44 44 68 92 92 92 116 140 164 164 188
Total Number of 3-State Buffers 704 1,504 2,464 4,640 4,896 6,848 9,696 11,808 16,544 16,544 22,048
Switch Matrix
Figure 45: Virtex-II Pro 3-State Buffers The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that timing is more predictable and less load dependant especially with larger devices.
3 - state lines
Switch matrix CLB-II
Programmable connection
Switch matrix CLB-II
DS031_09_032700
Figure 46: 3-State Buffer Connection to Horizontal Lines
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
CLB/Slice Configurations
Table 19 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be implemented in one of the configurations listed. Table 20 shows the available resources in all CLBs. Table 19: Logic Resources in One CLB Slices 4 LUTs 8 Flip-Flops 8 MULT_ANDs 8 Arithmetic & Carry-Chains 2 SOP Chains 2 Distributed SelectRAM+ 128 bits Shift Registers 128 bits TBUF 2
Table 20: Virtex-II Pro Logic Resources Available in All CLBs CLB Array: Row x Column 16 x 22 40 x 22 40 x 34 56 x 46 56 x 46 80 x 46 88 x 58 88 x 70 104 x 82 104 x 82 120 x 94 Number of Slices 1,408 3,008 4,928 9,280 9,792 13,696 19,392 23,616 33,088 33,088 44,096 Number of LUTs 2,816 6,016 9,856 18,560 19,584 27,392 38,784 47,232 66,176 66,176 88,192 Max Distributed SelectRAM or Shift Register (bits) 45,056 96,256 157,696 296,960 313,334 438,272 620,544 755,712 1,058,816 1,058,816 1,411,072 Number of Flip-Flops 2,816 6,016 9,856 18,560 18,560 27,392 38,784 47,232 66,176 66,176 88,192 Number of Carry-Chains (1) 44 44 68 92 92 92 116 140 164 164 188 Number of SOP Chains (1) 32 80 80 112 112 160 176 176 208 208 240
Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
Notes: 1. The carry-chains and SOP chains can be split or cascaded.
18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb block SelectRAM+ resources. These complement the distributed SelectRAM+ resources that provide shallow RAM structures implemented in CLBs. Each Virtex-II Pro block SelectRAM+ resource is an 18 Kb true dual-port RAM with two independently clocked and independently controlled synchronous ports that access a common storage area. Both ports are functionally identical. CLK, EN, WE, and SSR polarities are defined through configuration. Each port has the following types of inputs: Clock and Clock Enable, Write Enable, Set/Reset, and Address, as well as separate Data/parity data inputs (for write) and Data/parity data outputs (for read). Operation is synchronous; the block SelectRAM+ behaves like a register. Control, address and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. Data outputs change as a result of the same clock edge.
DS083 (v4.7) November 5, 2007 Product Specification
Configuration
Virtex-II Pro block SelectRAM+ supports various configurations, including single- and dual-port RAM and various data/address aspect ratios. Supported memory configurations for single- and dual-port modes are shown in Table 21. Table 21: Dual- and Single-Port Configurations 16K x 1 bit 8K x 2 bits 4K x 4 bits Single-Port Configuration As a single-port RAM, the block SelectRAM+ has access to the 18 Kb memory locations in any of the 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb memory locations in any of the 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations. The advantage of the 9-bit, 18-bit and 36-bit widths is the ability to store a parity bit for each eight bits. Parity bits must be generated or checked exter2K x 9 bits 1K x 18 bits 512 x 36 bits
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Dual-Port Configuration As a dual-port RAM, each port of block SelectRAM+ has access to a common 18 Kb memory resource. These are fully synchronous ports with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. Table 22 illustrates the different configurations available on ports A and B. If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18 Kb block is accessible from port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit block is accessible from Port A or Port B. All other configurations result in one port having access to an 18 Kb memory block and the other port having access to a 16 K-bit subset of the memory block equal to 16 Kbs.
nally in user logic. In such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored and behave exactly as the other bits, including the timing parameters. Video applications can use the 9-bit ratio of Virtex-II Pro block SelectRAM+ memory to advantage. Each block SelectRAM+ cell is a fully synchronous memory as illustrated in Figure 47. Input data bus and output data bus widths are identical.
18-Kbit Block SelectRAM DI DIP ADDR WE EN SSR CLK
DO DOP
DS031_10_102000
Figure 47: 18 Kb Block SelectRAM+ Memory in Single-Port Mode Table 22: Dual-Port Mode Configurations Port A Port B Port A Port B Port A Port B Port A Port B Port A Port B Port A Port B 16K x 1 16K x 1 8K x 2 8K x 2 4K x 4 4K x 4 2K x 9 2K x 9 1K x 18 1K x 18 512 x 36 512 x 36 16K x 1 8K x 2 8K x 2 4K x 4 4K x 4 2K x 9 2K x 9 1K x 18 1K x 18 512 x 36 16K x 1 4K x 4 8K x 2 2K x 9 4K x 4 1K x 18 2K x 9 512 x 36 16K x 1 2K x 9 8K x 2 1K x 18 4K x 4 512 x 36 16K x 1 1K x 18 8K x 2 512 x 36 16K x 1 512 x 36
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description ing or falling clock edge causes the data to be loaded into the memory cell addressed. A write operation performs a simultaneous read operation. Three different options are available, selected by configuration: 1. WRITE_FIRST The WRITE_FIRST option is a transparent mode. The same clock edge that writes the data input (DI) into the memory also transfers DI into the output registers DO, as shown in Figure 49.
Each block SelectRAM+ cell is a fully synchronous memory, as illustrated in Figure 48. The two ports have independent inputs and outputs and are independently clocked.
18-Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA
DOA DOPA
DIB DIPB ADDRB WEB ENB SSRB CLKB
Data_in
DI
Internal Memory
DO
Data_out = Data_in
CLK WE Data_in
DS031_11_102000
DOB DOPB
New aa Old New New
DS083-2_14_050901
Figure 48: 18 Kb Block SelectRAM+ in Dual-Port Mode Port Aspect Ratios Table 23 shows the depth and the width aspect ratios for the 18 Kb block SelectRAM+ resource. Virtex-II Pro block SelectRAM+ also includes dedicated routing resources to provide an efficient interface with CLBs, block SelectRAM+, and multipliers. Table 23: 18 Kb Block SelectRAM+ Port Aspect Ratio
Width 1 2 4 9 18 36 Depth 16,384 8,192 4,096 2,048 1,024 512 Address Bus ADDR[13:0] ADDR[12:0] ADDR[11:0] ADDR[10:0] ADDR[9:0] ADDR[8:0] Data Bus DATA[0] DATA[1:0] DATA[3:0] DATA[7:0] DATA[15:0] DATA[31:0] Parity Bus N/A N/A N/A Parity[0] Parity[1:0] Parity[3:0]
Address RAM Contents Data_out
Figure 49: WRITE_FIRST Mode 2. READ_FIRST The READ_FIRST option is a read-before-write mode. The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell addressed into the data output registers DO, as shown in Figure 50.
Internal Memory
Data_in
DI
DO
Prior stored data
CLK
Read/Write Operations
The Virtex-II Pro block SelectRAM+ read operation is fully synchronous. An address is presented, and the read operation is enabled by control signal ENA or ENB. Then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into output registers. The write operation is also fully synchronous. Data and address are presented, and the write operation is enabled by control signals WEA and WEB in addition to ENA or ENB. Then, again depending on the clock input mode, a ris-
WE Data_in Address RAM Contents Data_out New aa Old New Old
DS083-2_13_050901
Figure 50: READ_FIRST Mode
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Table 25 shows the number of columns as well as the total amount of block SelectRAM+ memory available for each Virtex-II Pro device. The 18 Kb SelectRAM+ blocks are cascadable to implement deeper or wider single- or dual-port memory resources. Table 25: Virtex-II Pro SelectRAM+ Memory Available Total SelectRAM+ Memory Device Columns 4 4 6 8 8 8 10 12 14 14 16 Blocks 12 28 44 88 136 88 192 232 328 308 444 in Kb 216 504 792 1,584 2,448 1,584 3,456 4,176 5,904 5,544 7,992 in Bits 221,184 516,096 811,008 1,622,016 2,506,752 1,622,016 3,538,944 4,276,224 6,045,696 5,677,056 8,183,808
3. NO_CHANGE The NO_CHANGE option maintains the content of the output registers, regardless of the write operation. The clock edge during the write mode has no effect on the content of the data output register DO. When the port is configured as NO_CHANGE, only a read operation loads a new value in the output register DO, as shown in Figure 51.
Data_in
DI
Internal Memory
DO
No change during write
XC2VP2 XC2VP4
CLK WE Data_in Address RAM Contents Data_out New aa Old New Last Read Cycle Content (no change)
DS083-2_12_050901
XC2VP7 XC2VP20 XC2VP30 XC2VPX20 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
Figure 51: NO_CHANGE Mode
Control Pins and Attributes
Virtex-II Pro SelectRAM+ memory has two independent ports with the control signals described in Table 24. All control inputs including the clock have an optional inversion. Table 24: Control Functions Control Signal CLK EN WE SSR Function Read and Write Clock Enable affects Read, Write, Set, Reset Write Enable Set DO register to SRVAL (attribute)
Figure 52 shows the layout of the block RAM columns in the XC2VP4 device.
RocketIO TM Serial Transceivers
DCM
DCM
BRAM Multiplier Blocks
CLBs
CLBs
Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the output register value after device configuration (INIT) and SSR is asserted (SRVAL). Both attributes (INIT_B and SRVAL) are available for each port when a block SelectRAM+ resource is configured as dual-port RAM.
CLBs
CLBs
CLBs
PPC405 CPU
Total Amount of SelectRAM+ Memory
Virtex-II Pro SelectRAM+ memory blocks are organized in multiple columns. The number of blocks per column depends on the row size, the number of Processor Blocks, and the number of RocketIO transceivers.
DCM
RocketIO TM Serial Transceivers
DCM
DS083-2_11_010802
Figure 52: XC2VP4 Block RAM Column Layout
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2's complement signed multiplier. Virtex-II Pro devices incorporate many embedded multiplier blocks. These multipliers can be associated with an 18 Kb block SelectRAM+ resource or can be used independently. They are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. Each SelectRAM+ memory and multiplier block is tied to four switch matrices, as shown in Figure 53.
A[17:0]
Multiplier Block
MULT 18 x 18 B[17:0]
P[35:0]
DS031_40_100400
Figure 54: Multiplier Block
Locations / Organization
Switch Matrix
Multiplier organization is identical to the 18 Kb SelectRAM+ organization, because each multiplier is associated with an 18 Kb block SelectRAM+ resource.
18 x 18 Multiplier
Table 26: Multiplier Resources Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 Columns 4 4 6 8 8 8 10 12 14 14 16 Total Multipliers 12 28 44 88 136 88 192 232 328 308 444
Switch Matrix 18-Kbit block SelectRAM Switch Matrix
Switch Matrix
XC2VP30 XC2VPX20
DS031_33_101000
XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
Figure 53: SelectRAM+ and Multiplier Blocks
Association With Block SelectRAM+ Memory
The interconnect is designed to allow SelectRAM+ memory and multiplier blocks to be used at the same time, but some interconnect is shared between the SelectRAM+ and the multiplier. Thus, SelectRAM+ memory can be used only up to 18 bits wide when the multiplier is used, because the multiplier shares inputs with the upper data bits of the SelectRAM+ memory. This sharing of the interconnect is optimized for an 18-bit-wide block SelectRAM+ resource feeding the multiplier. The use of SelectRAM+ memory and the multiplier with an accumulator in LUTs allows for implementation of a digital signal processor (DSP) multiplier-accumulator (MAC) function, which is commonly used in finite and infinite impulse response (FIR and IIR) digital filters.
In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs), page 35).
Global Clock Multiplexer Buffers
Virtex-II Pro devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads center on both the top edge and the bottom edge of the device, as illustrated in Figure 55. The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in Virtex-II Pro devices. Like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-bit-wide inputs, and the output is 36 bits. Figure 54 shows a multiplier block.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Each global clock multiplexer buffer can be driven either by the clock pad to distribute a clock directly to the device, or by the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 51. Each global clock multiplexer buffer can also be driven by local interconnects. The DCM has clock output(s) that can be connected to global clock multiplexer buffer inputs, as shown in Figure 56. Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in CLBs and IOBs, and SelectRAM+ blocks. Eight global clocks can be used in each quadrant of the Virtex-II Pro device. Designers should consider the clock distribution detail of the device prior to pin-locking and floorplanning. (See the Virtex-II Pro Platform FPGA User Guide.)
8 clock pads
Virtex-II Pro Device
8 clock pads
DS083-2_42_052902
Figure 55: Virtex-II Pro Clock Pads
Clock Pad
Clock Pad
CLKIN
DCM
CLKOUT
Local Interconnect
Clock Multiplexer I Clock Buffer
O Clock Distribution
DS083-2_43_122001
Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Figure 57 shows clock distribution in Virtex-II Pro devices. In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight down). To reduce power consumption, any unused clock branches remain static.
8 BUFGMUX
NW
NE
8
NW
8 BUFGMUX
NE
8
8 max
16 Clocks
8
16 Clocks
8
SW
8 BUFGMUX
SE
SW
SE
8 BUFGMUX
DS083-2_45_122001
Figure 57: Virtex-II Pro Clock Distribution Global clocks are driven by dedicated clock buffers (BUFG), which can also be used to gate the clock (BUFGCE) or to multiplex between two independent clock inputs (BUFGMUX). The most common configuration option of this element is as a buffer. A BUFG function in this (global buffer) mode, is shown in Figure 58.
BUFGCE
If the CE input is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming clock High time has no effect.
BUFGCE BUFG I O CE
DS031_61_101200 DS031_62_101200
I
O
Figure 59: Virtex-II Pro BUFGCE Function If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output.
Figure 58: Virtex-II Pro BUFG Function The Virtex-II Pro global clock buffer BUFG can also be configured as a clock enable/disable circuit (Figure 59), as well as a two-input clock multiplexer (Figure 60). A functional description of these two options is provided below. Each of them can be used in either of two modes, selected by configuration: rising clock edge or falling clock edge. This section describes the rising clock edge option. For the opposite option, falling clock edge, just change all "rising" references to "falling" and all "High" references to "Low", except for the description of the CE and S levels. The rising clock edge option uses the BUFGCE and BUFGMUX primitives. The falling clock edge option uses the BUFGCE_1 and BUFGMUX_1 primitives.
BUFGMUX
BUFGMUX can switch between two unrelated, even asynchronous clocks. Basically, a Low on S selects the I0 input, a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and Low time is never shorter than the shortest High or Low time of either input clock. As long as the presently selected clock is High, any level change of S has no effect.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description left and right I/O banks, Virtex-II Pro FPGAs can support up to 50 local clocks for DDR SDRAM. These interfaces can operate beyond 200 MHz on Virtex-II Pro devices.
BUFGMUX I0 I1 S
DS083-2_63_121701
O
Digital Clock Manager (DCM)
The Virtex-II Pro DCM offers a wide range of powerful clock management features. * Clock De-skew: The DCM generates new system clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, thus eliminating clock distribution delays. Frequency Synthesis: The DCM generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. Phase Shifting: The DCM provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control.
Figure 60: Virtex-II Pro BUFGMUX Function If the presently selected clock is Low while S changes, or if it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transition from High to Low. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock (I0 or I1). Violating this setup time requirement can result in an undefined runt pulse output. All Virtex-II Pro devices have 16 global clock multiplexer buffers. Figure 61 shows a switchover from I0 to I1.
Wait for Low S I0 Switch I1 Out
*
*
The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. It also utilizes fully digital feedback systems, operating dynamically to compensate for temperature and voltage variations during operation. Up to four of the nine DCM clock outputs can drive inputs to global clock buffers or global clock multiplexer buffers simultaneously (see Figure 62). All DCM clock outputs can simultaneously drive general routing resources, including routes to output buffers.
DCM
CLKIN CLKFB RST
DS083-2_46_020604
Figure 61: Clock Multiplexer Waveform Diagram * * * * * * The current clock is CLK0. S is activated High. If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. When CLK1 transitions from High to Low, the output switches to CLK1. No glitches or short pulses can appear on the output.
DSSEN
CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV
PSINCDEC CLKFX PSEN CLKFX180 PSCLK LOCKED STATUS[7:0] clock signal control signal PSDONE
DS031_67_112900
Figure 62: Digital Clock Manager The DCM can be configured to delay the completion of the Virtex-II Pro configuration process until after the DCM has achieved lock. This guarantees that the chip does not begin operating until after the system clocks generated by the DCM have stabilized.
Local Clocking
In addition to global clocks, there are local clock resources in the Virtex-II Pro devices. There are more than 72 local clocks in the Virtex-II Pro family. These resources can be used for many different applications, including but not limited to memory interfaces. For example, even using only the
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description which results in a clock output frequency four times faster than the clock input frequency (CLKIN). CLK2X180 is phase shifted 180 degrees relative to CLK2X. CLKFX180 is phase shifted 180 degrees relative to CLKFX. All frequency synthesis outputs automatically have 50/50 duty cycles, with the exception of the CLKDV output when performing a non-integer divide in high-frequency mode. See Table 28 for more details. Note that CLK2X and CLK2X180 are not available in high-frequency mode. Table 28: CLKDV Duty Cycle for Non-integer Divides CLKDV_DIVIDE 1.5 2.5 3.5 4.5 5.5 6.5 7.5 Duty Cycle 1/ 3 2/5 3/ 7 4/9 5 / 11 6 / 13 7 / 15
The DCM has the following general control signals: * * * RST input pin: resets the entire DCM LOCKED output pin: asserted High when all enabled DCM circuits have locked. STATUS output pins (active High): shown in Table 27.
Table 27: DCM Status Pins Status Pin 0 1 2 3 4 5 6 7 Function Phase Shift Overflow CLKIN Stopped CLKFX Stopped N/A N/A N/A N/A N/A
Clock De-skew
The DCM de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. Additional delay is introduced so that clock edges arrive at internal registers and block RAMs simultaneously with the clock edges arriving at the input clock pad. Alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. All DCM output clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. To achieve clock de-skew, connect the CLKFB input to CLK0. Note that CLKFB must always be connected, unless only the CLKFX or CLKFX180 outputs are used and de-skew is not required.
Phase Shifting
The DCM provides additional control over clock skew through either coarse or fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 63 illustrates the effects of fine-phase shifting. For more information on DCM features, see the Virtex-II Pro Platform FPGA User Guide. Table 29 lists fine-phase shifting control pins, when used in variable mode. Table 29: Fine Phase Shifting Control Pins Control Pin PSINCDEC PSEN PSCLK PSDONE Direction In In In Out Function Increment or decrement Enable phase shift Clock for phase shift Active when completed
Frequency Synthesis
The DCM provides flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output creates divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The CLKFX and CLKFX180 outputs can be used to produce clocks at the following frequency:
FREQ CLKFX = ( M D ) * FREQ CLKIN
where M and D are two integers. Specifications for M and D are provided under DCM Timing Parameters in Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. By default, M = 4 and D = 1,
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE
CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS negative) (PS/256) x PERIODCLKIN (PS positive)
CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB (PS/256) x PERIODCLKIN (PS positive)
DS031_48_110300
(PS/256) x PERIODCLKIN (PS negative)
Figure 63: Fine-Phase Shifting Effects Two separate components of the phase shift range must be understood: * *
PHASE_SHIFT attribute range FINE_SHIFT_RANGE DCM timing parameter range
since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: * If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. If PERIODCLKIN 0.5 * FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode.
The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified under DCM Timing Parameters in Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. Absolute range (fixed mode) = FINE_SHIFT_RANGE Absolute range (variable mode) = FINE_SHIFT_RANGE/2 The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, thus dividing the total delay line range in half. In fixed mode, Table 30: DCM Frequency Ranges Low-Frequency Mode Output Clock
CLK0, CLK180 CLK90, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180
*
*
Operating Modes
The frequency ranges of DCM input and output clocks depend on the operating mode specified, either low-frequency mode or high-frequency mode, according to Table 30. For actual values, see Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. The CLK2X, CLK2X180, CLK90, and CLK270 outputs are not available in high-frequency mode. High or low-frequency mode is selected by an attribute.
High-Frequency Mode CLKIN Input
CLKIN_FREQ_DLL_HF NA NA CLKIN_FREQ_DLL_HF CLKIN_FREQ_FX_HF
CLKIN Input
CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_FX_LF
CLK Output
CLKOUT_FREQ_1X_LF CLKOUT_FREQ_1X_LF CLKOUT_FREQ_2X_LF CLKOUT_FREQ_DV_LF CLKOUT_FREQ_FX_LF
CLK Output
CLKOUT_FREQ_1X_HF NA NA CLKOUT_FREQ_DV_HF CLKOUT_FREQ_FX_HF
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Routing
DCM and MGT Locations/Organization
Virtex-II Pro DCMs and serial transceivers (MGTs) are placed on the top and bottom of each block RAM and multiplier column in some combination, as shown in Table 31. The number of DCMs and RocketIO transceivers total twice the number of block RAM columns in the device. Refer to Figure 52, page 47 for an illustration of this in the XC2VP4 device. Table 31: DCM and MGT Organization Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Block RAM Columns 4 4 6 8 8 8 10 12 14 14 16 DCMs 4 4 4 8 8 8 8 8 8 8 12 MGTs 4 4 8 8 8 8 12 16 20 20 20 * Place-and-route software takes advantage of this regular array to deliver optimum system performance and fast compile times. The segmented routing resources are essential to guarantee IP cores portability and to efficiently handle an incremental design flow that is based on modular implementations. Total design time is reduced due to fewer and shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II Pro signals are routed using the global routing resources, which are located in horizontal and vertical routing channels between each switch matrix. As shown in Figure 64, page 54, Virtex-II Pro has fully buffered programmable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. Fanout has minimal impact on the performance of each net. * The long lines are bidirectional wires that distribute signals across the device. Vertical and horizontal long lines span the full height and width of the device. The hex lines route signals to every third or sixth block away in all four directions. Organized in a staggered pattern, hex lines can only be driven from one end. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source).
24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines
16 Direct Connections (total in all four directions)
8 Fast Connects
DS031_60_110200
Figure 64: Hierarchical Routing Resources
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description * Horizontal routing resources are provided for on-chip 3-state buses. Four partitionable bus lines are provided per CLB row, permitting multiple buses within a row. (See 3-State Buffers, page 43.) Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-chain MUXCY output signals vertically to the adjacent slice. (See CLB/Slice Configurations, page 44.) One dedicated SOP chain per slice row (two per CLB row) propagate ORCY output logic signals horizontally to the adjacent slice. (See Sum of Products, page 42.) One dedicated shift-chain per CLB connects the output of LUTs in shift-register mode to the input of the next LUT in shift-register mode (vertically) inside the CLB. (See Shift Registers, page 39.)
*
* *
The double lines route signals to every first or second block away in all four directions. Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). The direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. The fast connect lines are the internal CLB local interconnections from LUT outputs to LUT inputs.
*
*
Dedicated Routing
In addition to the global and local routing resources, dedicated signals are available. * There are eight global clock nets per quadrant. (See Global Clock Multiplexer Buffers, page 48.)
*
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Configuration
Virtex-II Pro devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general purpose inputs and outputs once configuration is complete. Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1, and M0 are dedicated pins. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to ground or VCCAUX. The mode pins should not be toggled during and after configuration. An additional pin, HSWAP_EN is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration. By default, HSWAP_EN is tied High (internal pull-up) which shuts off the pull-ups on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. Other dedicated pins are CCLK (the configuration clock pin), DONE, PROG_B, and the Boundary-Scan pins: TDI, TDO, TMS, and TCK. (The TDO pin is open-drain and does not have an internal pull-up resistor.) Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or an input accepting an externally generated clock. The configuration pins and Boundary-Scan pins are independent of the VCCO. The auxiliary power supply (VCCAUX) of 2.5V is used for these pins. All configuration pins are LVCMOS25 12mA. See Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics. A "persist" option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the Boundary-Scan related pins. The persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of configuration data. The CCLK pin on the FPGA is an input in this mode. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of the externally generated CCLK. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the falling edge of CCLK. Slave-serial mode is selected by applying [111] to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is the Virtex-II Pro FPGA device that drives the configuration clock on the CCLK pin to a Xilinx Serial PROM which in turn feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the falling CCLK edge. The interface is identical to slave serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the Virtex-II Pro FPGA device with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, an active Low Chip Select (CS_B) signal and a Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If RDWR_B is asserted, configuration data is read out of the FPGA as part of a readback operation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback using the persist option. Multiple Virtex-II Pro FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each device in turn and writing the appropriate data.
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Configuration Modes
Virtex-II Pro supports the following five configuration modes: * * * * * Slave-Serial Mode Master-Serial Mode Slave SelectMAP Mode Master SelectMAP Mode Boundary-Scan (JTAG, IEEE 1532) Mode
Refer to Table 32, page 57. A detailed description of configuration modes is provided in the Virtex-II Pro Platform FPGA User Guide.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description Virtex-II Pro device configuration using Boundary-Scan is compatible with with IEEE 1149.1-1993 standard and the new IEEE 1532 standard for In-System Configurable (ISC) devices. The IEEE 1532 standard is backward compliant with the IEEE 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-System Configurable (ISC) devices is intended to be programmed, reprogrammed, or tested on the board via a physical and logical protocol. Configuration through the Boundary-Scan port is always available, independent of the mode selection. Selecting the Boundary-Scan mode simply turns off the other modes.
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The device is configured byte-wide on a CCLK supplied by the Virtex-II Pro FPGA device. Timing is similar to the Slave SerialMAP mode except that CCLK is supplied by the Virtex-II Pro FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In Boundary-Scan mode, dedicated pins are used for configuring the Virtex-II Pro device. The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). Table 32: Virtex-II Pro Configuration Mode Pin Settings Configuration Mode (1) Master Serial Slave Serial Master SelectMAP Slave SelectMAP Boundary-Scan M2 0 1 0 1 1 M1 0 1 1 1 0
M0 0 1 1 0 1
CCLK Direction Out In Out In N/A
Data Width 1 1 8 8 1
Serial DOUT (2) Yes Yes No No No
Notes: 1. The HSWAP_EN pin controls the pull-ups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pull-ups are used. 2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices.
Table 33 lists the default total number of bits required to configure each device. Table 33: Virtex-II Pro Default Bitstream Lengths Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Number of Configuration Bits 1,305,376 3,006,496 4,485,408 8,214,560 8,214,560 11,589,920 15,868,192 19,021,344 26,098,976 26,098,976 34,292,768
Configuration is automatically initiated on power-up unless it is delayed by the user. The INIT_B pin can be held Low using an open-drain driver. An open-drain is required since INIT_B is a bidirectional open-drain pin that is held Low by a Virtex-II Pro FPGA device while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is signaled by the INIT_B pin going High, and the completion of the entire process is signaled by the DONE pin going High. The Global Set/Reset (GSR) signal is pulsed after the last frame of configuration data is written but before the start-up sequence. The GSR signal resets all flip-flops on the device. The default start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Write Enable (GWE) signal is released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed via configuration options in software. In addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start
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Configuration Sequence
The configuration of Virtex-II Pro devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description ured with the corresponding encrypted bitstream, using any of the configuration modes described previously. A detailed description of how to use bitstream encryption is provided in the Virtex-II Pro Platform FPGA User Guide. Your local FAE can also provide specific information on this feature.
synchronously. The sequence can also be paused at any stage, until lock has been achieved on any or all DCMs, as well as DCI.
Readback
In this mode, configuration data from the Virtex-II Pro FPGA device can be read back. Readback is supported only in the SelectMAP (master and slave) and Boundary-Scan mode. Along with the configuration data, it is possible to read back the contents of all registers, distributed SelectRAM+, and block RAM resources. This capability is used for real-time debugging. For more detailed configuration information, see the Virtex-II Pro Platform FPGA User Guide.
Partial Reconfiguration
Partial reconfiguration of Virtex-II Pro devices can be accomplished in either Slave SelectMAP mode or Boundary-Scan mode. Instead of resetting the chip and doing a full configuration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. Data is loaded on a column basis, with the smallest load unit being a configuration "frame" of the bitstream (device size dependent). Partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. For more information on Partial Reconfiguration in Virtex-II Pro devices, please refer to Xilinx Application Note XAPP290, Two Flows for Partial Reconfiguration.
Bitstream Encryption
Virtex-II Pro devices have an on-chip decryptor using one or two sets of three keys for triple-key Data Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the configuration data (bitstream) with a triple-key DES determined by the designer. The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin, when the device is not powered. Virtex-II Pro devices can be config-
Revision History
This section records the change history for this module of the data sheet. Date 01/31/02 06/13/02 09/03/02 Version 1.0 2.0 2.1 Initial Xilinx release. New Virtex-II Pro family members. New timing parameters per speedsfile v1.62. * * * * * * * * 12/03/02 01/20/03 2.4 2.5 * * * * Revised Reset and Power sections. Updated Table 8, which lists compatible input standards. [Table deleted in v2.6.] Added Figure 28, Figure 29, and Figure 30, which provide examples illustrating the use of I/O standards. In section RocketIO Overview, corrected max number of MGTs from 16 to 24. In section Input/Output Blocks (IOBs), added references to XAPP653 regarding implementation of 3.3V I/O standards. Table 8: Added rows for LVTTL, LVCMOS33, and PCI-X. Table 8: Added LVTTL and LVCMOS33 to compatible 3.3V cells. [Table deleted in v2.6.] Table 33: Correct bitstream lengths. Added mention of LVTTL and PCI with respect to SelectIO-Ultra configurations. See section Input/Output Individual Options and Figure 22. Added qualification to features vs. Virtex-II (open-drain output pin TDO does not have internal pull-up resistor) Table 7: Added HSTL18 (I, II, III, & IV) and HSTL18_DCI (I,II, III & IV) to 1.8V VCCO row. [Table deleted in v2.6.] Table 8: Numerous revisions. [Table deleted in v2.6.] Revision
09/27/02
2.2
11/20/02
2.3
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Date 03/24/03
Version 2.5.1 * *
Revision Table 10: Corrected I/O standard names SSTL18_I and SSTL18_II to SSTL18_I_DCI and SSTL18_II_DCI respectively. Figure 61, text below: Corrected wording of criteria for clock switching. Removed Compatible Output Standards and Compatible Input Standards tables. Added new Table 12, Summary of Voltage Supply Requirements for All Input and Output Standards. This table replaces deleted I/O standards tables. Corrected sentence in section Input/Output Individual Options, page 27, to read "The optional weak-keeper circuit is connected to each user I/O pad." Added section Rules for Combining I/O Standards in the Same Bank, page 29. Added four Differential Termination I/O standards to Table 9 and Table 12. Added section On-Chip Differential Termination and Figure 31, page 34. Added footnote referring to XAPP659 to 3.3V I/O callouts in Table 8 and Table 12. Section Configuration, page 56: Added text indicating that the mode pins M0-M2 must be held to a constant DC level during and after configuration. Deleted section Functional Description: RocketIO Multi-Gigabit Transceiver (MGT), page 10. Added section Local Clocking, page 51. Sections Slave-Serial Mode and Master-Serial Mode, page 56: Changed "rising" to "falling" edge with respect to DOUT. Table 8, page 24 and Table 10, page 25: Corrected Input VREF for HSTL_III-IV_18 from 1.08V to 1.1V. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, are released to Production status. Section BUFGMUX, page 50: Corrected the definition of the "presently selected clock" to be I0 or I1. Corrected signal names in Figure 61 and associated text from CLK0 and CLK1 to I0 and I1. Recompiled for backward compatibility with Acrobat 4 and above. No content changes. Section Clock De-skew, page 52: Removed reference to CLK2X as an option for DCM clock feedback.
05/27/03
2.6
* * * *
06/02/03 08/25/03 09/10/03 10/14/03
2.7 2.7.1 2.8 2.9
* * * * * * *
12/10/03 02/19/04
3.0 3.1
* *
03/09/04 04/22/04 06/30/04 11/17/04
3.1.1 3.2 4.0 4.1
* *
Merged in DS110-2 (Module 2 of Virtex-II Pro X data sheet). Separate RocketIO and RocketIO X sections created. * * * * * * * Figure 11, page 12: Corrected figure by removing coupling capacitors from input. Section Rules for Combining I/O Standards in the Same Bank, page 29: Corrected I/O standard in the first example from LVDS_25_DCI to LVDS_25. Reassigned heading hierarchies for better agreement with content. Table 7: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and AVCCAUXRX respectively. Table 9: Corrected VOD (output voltage) range for LVDSEXT_25. Table 25: Corrected SelectRAM+ memory available for XC2VPX70 device. Table 33: Updated configuration default bitstream lengths.
03/01/05
4.2
06/20/05 09/15/05
4.3 4.4
No changes in Module 2 for this revision. * * * * Table 1: Deleted SONET OC-192 protocol. Table 3: Deleted RocketIO X primitives for SONET OC-192, 10 Gbit Ethernet, and Xilinx 10G (Aurora) protocols. Changed all instances of 10.3125 Gb/s to 6.25 Gb/s. Table 7: Changed RocketIO X VCCAUXRX from 1.5V globally to 1.5V for 8B/10B encoding, 1.8V for all other encoding protocols.
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Date 10/10/05 03/05/07 11/05/07
Version 4.5 4.6 4.7 *
Revision Changed XC2VPX70 variable baud rate specification to fixed-rate operation at 4.25 Gb/s. Updated copyright notice and legal disclaimer. Debug Interface, page 19, and Boundary-Scan (JTAG, IEEE 1532) Mode, page 57: Updated IEEE 1149.1 compliance statement.
No changes in Module 2 for this revision. * *
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules: * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview (Module 1) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description (Module 2) * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics (Module 3) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information (Module 4)
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Product Specification
DS083 (v4.7) November 5, 2007
Virtex-II Pro(1) Electrical Characteristics
VirtexTM-II Pro devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance. Virtex-II Pro DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -6 speed grade industrial device are the same as for a -6 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information. All specifications are subject to change without notice.
Virtex-II Pro DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
VCCINT VCCAUX VCCO VBATT VREF VIN VTS
AVCCAUXRX AVCCAUXTX
Description(1)
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage 3.3V I/O input voltage relative to GND (user and dedicated I/Os) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) Voltage applied to 3-state 3.3V output (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os) Receive auxilliary supply voltage relative to GNDA (analog ground) Transmit auxilliary supply voltage relative to GNDA (analog ground) Terminal receive supply voltage relative to GND Terminal transmit supply voltage relative to GND Storage temperature (ambient) All regular FG/FF flip-chip packages
Virtex-II Pro X
Virtex-II Pro
Units
V V V V V V V V V V V V V C C C C C
-0.5 to 1.6 -0.5 to 3.0 -0.5 to 3.75 -0.5 to 4.05 -0.3 to 3.75 -0.3 to 4.05 (3) -0.5 to VCCO + 0.5 -0.3 to 4.05 (3) -0.5 to VCCO + 0.5 -0.5 to 2.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 1.6 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 3.0
VTRX VTTX TSTG
-65 to +150 +220 N/A N/A +125 +260 +250
TSOL
Maximum soldering temperature (2) Maximum junction temperature (2)
Pb-free FGG256 wire-bond package Pb-free FGG456 and FGG676 wire-bond packages
TJ
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see the Device Packaging and Thermal Characteristics Guide information on the Xilinx website. 3. 3.3V I/O Absolute Maximum limit applied to DC and AC signals. Refer to XAPP659 for more details.
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
(c) 2002-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Table 2: Recommended Operating Conditions Virtex-II Pro X Symbol Description
Internal supply voltage relative to GND, TJ = 0 C to +85C VCCINT Internal supply voltage relative to GND, TJ = -40C to +100C
Virtex-II Pro Min
1.425 1.425 2.375 2.375 1.2 1.2 GND - 0.2 GND - 0.2 GND - 0.2 GND - 0.2 1.0 1.0 2.375 2.375 2.375 2.375 1.6 1.6 1.6 1.6
Grade
Comm. Indus.
Min
1.425 1.425 2.375 2.375 1.2 1.2 GND - 0.2 GND - 0.2 GND - 0.2 GND - 0.2 1.0 1.0
Max
1.575 1.575 2.625 2.625 3.45 (5) 3.45 (5) 3.45 (5) 3.45 (5) VCCO + 0.2 VCCO + 0.2 3.6 3.6
Max
1.575 1.575 2.625 2.625 3.45 (5) 3.45 (5) 3.45 (5) 3.45 (5) VCCO + 0.2 VCCO + 0.2 3.6 3.6 2.625 2.625 2.625 2.625 2.625 2.625 2.625 2.625
Units
V V V V V V V V V V V V V V V V V V V V
Auxiliary supply voltage relative to GND, TJ = 0 C to +85C Comm. VCCAUX(1) Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C 3.3V supply voltage relative to GND, TJ = 0 C to +85C 3.3V supply voltage relative to GND, TJ = -40C to +100C VIN 2.5V and below supply voltage relative to GND, TJ = 0 C to +85C 2.5V and below supply voltage relative to GND, TJ = -40C to +100C VBATT(4) Battery voltage relative to GND, TJ = 0 C to +85C Battery voltage relative to GND, TJ = -40C to +100C Auxilliary receive supply voltage relative to GNDA Indus. Comm.
AVCCAUXTX(6)
Indus. Comm. Indus. Comm. Indus. Comm. Indus. Comm. Indus.
VCCO(2,3)
Comm. 1.425 (7) 1.575 (7)
AVCCAUXRX(6)
1.425 (7) 1.575 (7) 2.375 2.375 0 0 1.425 1.425 2.625 2.625 2.625 2.625 1.575 1.575
Auxilliary transmit supply voltage relative to GNDA Indus. Comm.
VTRX
Terminal receive supply voltage relative to GND Indus. Comm. Terminal transmit supply voltage relative to GND Indus.
VTTX
Notes: 1. Recommended maximum voltage droop for VCCAUX is 10 mV/ms. 2. Configuration data is retained even if VCCO drops to 0V. 3. For 3.3V I/O operation, refer to XAPP659, available on the Xilinx website at www.xilinx.com. 4. If battery is not used, connect VBATT to GND or VCCAUX. 5. For PCI and PCI-X, refer to XAPP653, available on the Xilinx website at www.xilinx.com. 6. IMPORTANT! The RocketIO transceivers have certain power guidelines that must be met, even if unused in the design. Please refer to the section entitled "Powering the RocketIO Transceivers" in the RocketIO Transceiver User Guide or RocketIO X Transceiver User Guide for more details. 7. For non-8B/10B-encoded data, the specification for AVCCAUXRX is 1.8V 5% (1.71 - 1.89V).
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Table 3: DC Characteristics Over Recommended Operating Conditions
Virtex-II Pro X Symbol
VDRINT VDRI IREF IL CIN IRPU IRPD IBATT (1) I CCAUXTX I CCAUXRX
Virtex-II Pro Min
1.25 2.0
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF current per pin Input or output leakage current per pin (sample-tested) Input capacitance (sample-tested) Pad pull-up (when selected) @ Vin = 0V, VCCO = 2.5V (sample tested) Pad pull-down (when selected) @ Vin = 2.5V (sample-tested) Battery supply current Operating AVCCAUXTX supply current Operating AVCCAUXRX supply current Operating ITTX supply current when transmitter is AC-coupled
Min
1.25 2.0
Typ
Max
Typ
Max
Units
V V
10 10 10 150 150
Note (2) Note (2)
10 10 10 150 150
A A pF A A nA
115 85 55 N/A N/A 15 N/A N/A 0.9 N/A N/A 290 310 450 525 N/A N/A N/A N/A N/A
60 35 30 15
105 75
mA mA mA mA mA
ITTX
Operating ITTX supply current when transmitter is DC-coupled Operating ITRX supply current when receiver is AC-coupled Operating ITRX supply current when receiver is DC-coupled Power dissipation of PowerPC TM 405 processor block Power dissipation of MGT @ 1.25 Gb/s per channel Power dissipation of MGT @ 2.5 Gb/s per channel
ITRX
15 0.9 230 310 350 N/A N/A N/A N/A mW/ MHz mW mW mW mW mW
PCPU
PRXTX (3)
Power dissipation of MGT @ 3.125 Gb/s per channel Power dissipation of MGT @ 4.25 Gb/s per channel Power dissipation of MGT @ 6.25 Gb/s per channel
Notes: 1. Characterized, not tested. 2. Battery supply current (IBATT):
Device Unpowered 25C: 85C: < 50 N/A Device Powered < 10 < 10 Units nA nA
3. Total dissipation of fully operational PMA and PCS combined. This power is the average power supply dissipation per MGT. The averaging was done by simultaneously turning on all eight transceivers and dividing the total power supply dissipation by eight.
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Table 4: Quiescent Supply Current Symbol Description Device
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 ICCINTQ Quiescent VCCINT supply current XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 ICCOQ Quiescent VCCO supply current XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 ICCAUXQ Quiescent VCCAUX supply current XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
Typ (1)
20 30 35 40 40 50 60 70 85 85 100 1.0 1.0 1.0 1.25 1.25 1.25 1.25 1.5 1.5 1.5 1.75 5 5 5 10 10 10 10 20 20 20 20
Max
300 400 500 600 600 800 1050 1250 1700 1700 2200 8.0 8.0 8.0 10 10 10 10 12 12 12 15 50 50 50 75 75 75 75 100 100 100 125
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes: 1. Typical values are specified at nominal voltage, 25 C. 2. Quiescent current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade values by 1.5. 3. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 4. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWERTM.
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Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. The VCCINT power supply must ramp on, monotonically, no faster than 200 s and no slower than 50 ms. Ramp-on is defined as: 0 VDC to minimum supply voltages (see Table 2). VCCAUX and VCCO can power on at any ramp rate. Power supplies can be turned on in any sequence. Table 5: Power-On Current for Virtex-II Pro Devices
Device
Table 5 shows the minimum current required by Virtex-II Pro devices for proper power-on and configuration. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. Once initialized and configured, use the power calculator to estimate current drain on these supplies. For more information on VCCAUX, VCCO, and configuration mode, refer to Chapter 3 in the Virtex-II Pro Platform FPGA User Guide.
Symbol ICCINTMIN ICCAUXMIN ICCOMIN
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
Units
500 250 100
500 250 100
500 250 100
600 250 100
600 250 100
800 250 100
1050 250 100
1250 250 100
1700 250 100
1700 250 100
2200 250 100
mA mA mA
Notes: 1. Power-on current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade values by 1.5. 2. ICCOMIN values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential. Consult Xilinx Application Note XAPP623 for detailed information on power distribution system design. VCCAUX powers critical resources in the FPGA. Therefore, this supply voltage is especially susceptible to power supply noise. VCCAUX can share a power plane with VCCO , but only if VCCO does not have excessive noise. Staying within simultaneously switching output (SSO) limits is essential for keeping power supply noise to a minimum. Refer to
XAPP689, "Managing Ground Bounce in Large FPGAs," to determine the number of simultaneously switching outputs allowed per bank at the package level.
Changes in VCCAUX voltage beyond 200 mV peak-to-peak should take place at a rate no faster than 10 mV per millisecond. Recommended practices that can help reduce jitter and period distortion are described in Xilinx Answer Record 13756.
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SelectIO-Ultra DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are choTable 6: DC Input and Output Levels
IOSTANDARD Attribute
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX GTLP GTL HSTL_I HSTL_II HSTL_III HSTL_IV SSTL2_I SSTL2_II SSTL18_I SSTL18_II
sen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
VOL V, max
3.45 3.45 VCCO + 0.4 VCCO + 0.4 VCCO + 0.4 3.6 3.6
Note (1)
VIL V, min
-0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2
VIH V, min
2.0 2.0 1.7 70% VCCO 70% VCCO 50% VCCO 50% VCCO
Note (1)
VOH V, min
2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 VCCO - 0.45 90% VCCO 90% VCCO
Note (1)
IOL mA
24 24 24 16 16
IOH mA
-24 -24 -24 -16 -16
V, max
0.8 0.8 0.7 30% VCCO 30% VCCO 30% VCCO 30% VCCO
Note (1)
V, max
0.4 0.4 0.4 0.4 0.4 10% VCCO 10% VCCO
Note (1)
Note (1)
Note (1)
VREF - 0.1 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.15 VREF - 0.15 VREF - 0.125 VREF - 0.125
VREF + 0.1 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.15 VREF + 0.15 VREF + 0.125 VREF + 0.125
VCCO + 0.4 VCCO + 0.4 VCCO + 0.4 VCCO + 0.4 VCCO + 0.4 VCCO + 0.4 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3
0.6 0.4 0.4(2) 0.4(2) 0.4(2) 0.4(2) VTT - 0.61 VTT - 0.81 VTT - 0.61 VTT - 0.61
n/a n/a VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.61 VTT + 0.81 VTT + 0.61 VTT + 0.61
36 40 8(2) 16(2) 24(2) 48(2) 8.1 16.2 6.7 13.4
n/a n/a -8(2) -16(2) -8(2) -8(2) -8.1 -16.2 -6.7 -13.4
Notes: 1. Tested according to relevant specifications. 2. This applies to 1.5V and 1.8V HSTL.
LDT DC Specifications (LDT_25)
Table 7: LDT DC Specifications
DC Parameter Supply Voltage Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOS Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude DS083 (v4.7) November 5, 2007 Product Specification Symbol VCCO VOD VOD VOCM VOCM VID VID VICM VICM RT = 100 ohm across Q and Q signals RT = 100 ohm across Q and Q signals Conditions Min 2.38 495 -15 495 -15 200 -15 440 -15 600 600 600 Typ 2.5 600 Max 2.63 715 15 715 15 1000 15 780 15 Units V mV mV mV mV mV mV mV mV
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LVDS DC Specifications (LVDS_25)
Table 8: LVDS DC Specifications
DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV 0.898 247 1.125 100 0.3 350 1.250 350 1.2 454 1.375 600 2.2 Conditions Min 2.38 Typ 2.5 Max 2.63 1.602 Units V V V mV V mV V
Extended LVDS DC Specifications (LVDSEXT_25)
Table 9: Extended LVDS DC Specifications
DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV 0.715 440 1.125 100 0.3 1.2 1.250 820 1.375 1000 2.2 Conditions Min 2.38 Typ 2.5 Max 2.63 1.785 Units V V V mV V mV V
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower Table 10: LVPECL DC Specifications
VCCO = 2.375V DC Parameter VOH VOL VIH VIL Differential Input Voltage Min 1.35 0.565 0.8 0.5 0.100 Max 1.495 0.755 2.0 1.7 1.5 VCCO = 2.5V Min 1.475 0.69 0.8 0.5 0.100 Max 1.62 0.88 2.0 1.7 1.5 VCCO = 2.625V Min 1.6 0.815 0.8 0.5 0.100 Max 1.745 1.005 2.0 1.7 1.5 Units V V V V V
common-mode ranges. Table 10 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-II Pro Platform FPGA User Guide.
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RocketIO DC Input and Output Levels
Table 11: RocketIO X Input/Output Voltage Specifications Parameter
Peak-to-Peak Differential Input Voltage (1) Single-Ended Output Voltage Swing (2,3)
Symbol
DVIN DVOUT DVPPOUT
Conditions
Min
250 0 0
Typ
Max
2000
Units
mV mV mV
400 800
900 1800
Peak-to-Peak Differential Output Voltage (2,3)
Notes: 1. See Table 24, page 15, for minimum eye sensitivity. 2. Output swing levels are selectable using TXDOWNLEVEL attribute. Refer to the RocketIO X Transceiver User Guide for details. 3. Output preemphasis levels are selectable using the TXEMPHLEVEL attribute. Refer to the RocketIO X Transceiver User Guide for details.
Table 12: RocketIO Input/Output Voltage Specifications Parameter
Peak-to-Peak Differential Input Voltage Differential Input Impedance Single-Ended Output Voltage Swing (1,2)
Symbol
DVIN
Conditions
Min
175
Typ
Max
2000 125 187.5 800
Units
mV mV mV
TERMINATION_IMP = 50 DIMPIN DVOUT DVPPOUT TERMINATION_IMP = 75
90 135 400 800 800
Peak-to-Peak Differential Output Voltage (1,2)
1600
Notes: 1. Output swing levels are selectable using TX_DIFF_CTRL attribute. Refer to the RocketIO Transceiver User Guide for details. 2. Output preemphasis levels are selectable at 10% (default), 20%, 25%, and 33% using the TX_PREEMPHASIS attribute. Refer to the RocketIO Transceiver User Guide for details.
+V
TXP DVOUT
DS083-3_04_120302
TXN 0
Figure 1: Single-Ended Output Voltage Swing
+V
0
DVPPOUT
-V
TXP-TXN
Figure 2: Peak-to-Peak Differential Output Voltage
DS083-3_05_120302
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Virtex-II Pro Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-II Pro devices. The numbers reported here are fully characterized worst-case values. Note that these values are subject to the same guidelines as Virtex-II Pro Switching Characteristics (speed files). Table 13: Pin-to-Pin Performance Description Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Combinatorial (pad to LUT to pad) Memory: Block RAM Pad to setup Clock to Pad Distributed RAM Pad to setup Clock to Pad XC2VP20FF1152-6 XC2VP20FF1152-6 1.78 4.12 ns ns XC2VP20FF1152-6 XC2VP20FF1152-6 1.72 6.63 ns ns XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 7.20 8.08 8.15 3.85 7.24 7.30 7.64 3.26 ns ns ns ns ns ns ns ns Device Used & Speed Grade Pin-to-Pin Performance (with I/O Delays) Units Table 13 provides pin-to-pin values (in nanoseconds) including IOB delays; that is, delay through the device from input pin to output pin. In the case of multiple inputs and outputs, the worst delay is reported.
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Table 14 shows internal (register-to-register) performance. Values are reported in MHz. Table 14: Register-to-Register Performance Description Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register to LUT to Register 8-bit Adder 16-bit Adder 32-bit Adder 64-bit Adder 128-bit Adder 24-bit Counter 64-bit Counter 64-bit Accumulator Multiplier 18x18 (with Block RAM inputs) Multiplier 18x18 (with Register inputs) Memory: Block RAM Single-Port 4096 x 4 bits Distributed RAM Single-Port 16 x 8-bit Single-Port 32 x 8-bit Single-Port 64 x 8-bit Single-Port 128 x 8-bit Dual-Port 16 x 8-bit Dual-Port 32 x 8-bit Dual-Port 64 x 8-bit XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 555 557 408 336 549 460 407 MHz MHz MHz MHz MHz MHz MHz XC2VP20FF1152-6 355 MHz XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 XC2VP20FF1152-6 547 392 310 710 609 472 400 1046 337 334 252 202 131 309 207 150 135 147 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Device Used & Speed Grade Register-to-Register Performance Units
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Virtex-II Pro Switching Characteristics
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Note that Virtex-II Pro Performance Characteristics are subject to these guidelines, as well. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Virtex-II Pro device with a corresponding speed file designation. All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Table 15: Virtex-II Pro Device Speed Grade Designations Speed Grade Designations Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 -6, -5 -6, -5 -6, -5 -7, -6, -5 -7, -6, -5 -7, -6, -5 -7, -6, -5 Advance Preliminary Production -7, -6, -5 -7, -6, -5 -7, -6, -5 -7, -6, -5
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-II Pro devices.
PowerPC Switching Characteristics
Table 16: Processor Clocks Absolute AC Characteristics Speed Grade -7 Description CPMC405CLOCK frequency JTAGC405TCK PLBCLK (3) BRAMDSOCMCLK (3) BRAMISOCMCLK (3) frequency (2) Min 0 0 0 0 0 Max 400 (1) 200 400 400 400 Min 0 0 0 0 0 -6 Max 350 (1) 175 350 350 350 Min 0 0 0 0 0 -5 Max 300 150 300 300 300 Units MHz MHz MHz MHz MHz
Notes: 1. IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than 300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, "PowerPC 405 Clock Macro for -7(C) and -6(I) Speed Grade Dual-Processor Devices." Refer to Table 1, Module 1 to identify dual-processor devices. 2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is dependent on the system, and will be much less. 3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. However, the achievable maximum is dependent on the system. Please see PowerPC 405 Processor Block Reference Guide and XAPP640 for more information.
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Table 17: Processor Block Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (CPMC405CLOCK) Device Control Register Bus control inputs Device Control Register Bus data inputs Clock and Power Management control inputs Reset control inputs Debug control inputs Trace control inputs External Interrupt Controller control inputs Clock to Out Device Control Register Bus control outputs Device Control Register Bus address outputs Device Control Register Bus data outputs Clock and Power Management control outputs Reset control outputs Debug control outputs Trace control outputs Clock CPMC405CLOCK minimum pulse width, high CPMC405CLOCK minimum pulse width, low TCPWH TCPWL 1.25 1.25 1.42 1.42 1.66 1.66 ns, min ns, min TPCKCO_DCR TPCKAO_DCR TPCKDO_DCR TPCKCO_CPM TPCKCO_RST TPCKCO_DBG TPCKCO_TRC 1.32 1.72 1.76 1.26 1.32 1.94 1.35 1.52 1.98 2.02 1.45 1.51 2.22 1.56 1.67 2.17 2.22 1.59 1.66 2.44 1.71 ns, max ns, max ns, max ns, max ns, max ns, max ns, max TPCCK_DCR/TPCKC_DCR TPDCK_DCR/TPCKD_DCR TPCCK_CPM/TPCKC_CPM TPCCK_RST/TPCKC_RST TPCCK_DBG/TPCKC_DBG TPCCK_TRC/TPCKC_TRC TPCCK_EIC/TPCKC_EIC 0.38/-0.18 0.65/-0.01 0.16/ 0.03 0.16/ 0.03 0.27/ 0.30 1.37/-0.41 0.57/-0.22 0.44/-0.20 0.75/-0.01 0.19/ 0.03 0.19/ 0.03 0.31/ 0.35 1.57/-0.48 0.66/-0.25 0.48/-0.23 0.82/-0.02 0.20/ 0.03 0.20/ 0.03 0.34/ 0.38 1.73/-0.52 0.72/-0.27 ns, min ns, min ns, min ns, min ns, min ns, min ns, min
Symbol
-7
-6
-5
Units
Table 18: Processor Block PLB Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (PLBCLK) Processor Local Bus(ICU/DCU) control inputs Processor Local Bus (ICU/DCU) data inputs Clock to Out Processor Local Bus(ICU/DCU) control outputs Processor Local Bus(ICU/DCU) address bus outputs Processor Local Bus(ICU/DCU) data bus outputs TPCKCO_PLB TPCKAO_PLB TPCKDO_PLB 1.34 1.16 1.44 1.54 1.34 1.65 1.69 1.47 1.81 ns, max ns, max ns, max TPCCK_PLB/TPCKC_PLB TPDCK_PLB/TPCKD_PLB 0.98/ 0.18 0.62/ 0.16 1.12/ 0.21 0.71/ 0.18 1.23/ 0.23 0.78/ 0.20 ns, min ns, min
Symbol
-7
-6
-5
Units
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Table 19: Processor Block JTAG Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs JTAG reset input Clock to Out JTAG control outputs TPCKCO_JTAG 1.34 1.54 1.69 ns, max TPCCK_JTAG/ TPCKC_JTAG TPCCK_JTAGRST/ TPCKC_JTAGRST 0.80/ 0.70 0.80/ 0.70 0.80/ 0.70 0.80/ 0.70 0.88/ 0.77 0.88/ 0.77 ns, min ns, min
Symbol
-7
-6
-5
Units
Table 20: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs Clock to Out Data-Side On-Chip Memory control outputs Data-Side On-Chip Memory address bus outputs Data-Side On-Chip Memory data bus outputs TPCKCO_DSOCM TPCKAO_DSOCM TPCKDO_DSOCM 1.58 1.46 0.90 1.82 1.68 1.03 1.99 1.84 1.13 ns, max ns, max ns, max TPDCK_DSOCM/ TPCKD_DSOCM 0.73/ 0.83 0.84/ 0.95 0.92/ 1.05 ns, min
Symbol
-7
-6
-5
Units
Table 21: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (BRAMISOCMCLK) Instruction-Side On-Chip Memory data bus inputs Clock to Out Instruction-Side On-Chip Memory control outputs Instruction-Side On-Chip Memory address bus outputs Instruction-Side On-Chip Memory data bus outputs TPCKCO_ISOCM TPCKAO_ISOCM TPCKDO_ISOCM 1.33 1.52 1.35 1.53 1.75 1.55 1.68 1.92 1.70 ns, max ns, max ns, max TPDCK_ISOCM/ TPCKD_ISOCM 0.81/ 0.68 0.93/ 0.78 1.02/ 0.86 ns, min
Symbol
-7
-6
-5
Units
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RocketIO Switching Characteristics
Table 22: RocketIO X Reference Clock Switching Characteristics
All Speed Grades Description
Reference Clock frequency Reference Clock rise time Reference Clock fall time Reference Clock duty cycle Reference Clock total jitter, peak-peak Clock recovery frequency acquisition time, from Power-up to High state of PMARXLOCK Clock recovery phase acquisition time, from Data to High state of PMARXLOCK range(1) Reference Clock frequency tolerance
Symbol
FGCLK FGTOL TRCLK TFCLK TDCREF TGJTT TLOCK TPHASE
Conditions
Min
62.5
Typ
Max
425 350
Units
MHz ppm ps ps
20% - 80% 20% - 80% 45 3.125 Gb/s - 6.25 Gb/s 2.488 Gb/s - 3.125 Gb/s
75 75 50 55 30 40 100 40 60
% ps ps s s
Notes: 1. BREFCLK should be used for all serial bit rates up to the maximum shown.
Table 23: RocketIO Reference Clock Switching Characteristics
All Speed Grades Description
Reference Clock frequency range(1) Reference Clock frequency tolerance Reference Clock rise time Reference Clock fall time Reference Clock duty cycle Reference Clock total jitter, peak-peak (3) Clock recovery frequency acquisition time Clock recovery phase acquisition time Notes:
1. 2. 3. 4. BREFCLK/BREFCLK2 can be used for all serial bit rates up to the maximum shown. REFCLK/REFCLK2 can be used for serial bit rates up to 2.5 Gb/s (REFCLK = 125 MHz). All other parameters apply equally to REFCLK, REFCLK2, BREFCLK, and BREFCLK2 except as noted. For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in XAPP572 are required to meet the transmit jitter and receive jitter tolerance specifications defined in this data sheet. Measured at the package pin. For reference clock frequencies equal to or above 125 MHz, BREFCLK/BREFCLK2 must be used. 8B/10B-type bitstream.
Symbol
FGCLK FGTOL TRCLK TFCLK TDCREF
Conditions
Full rate operation Half rate (2X oversampling) 20% - 80% 20% - 80% operation(2)
Min
50 60
Typ
Max
156.25 100 100
Units
MHz MHz ppm ps ps % ps ps ps s bits (4)
600 600 45 50
1000 1000 55 40 50 120 10
2.501 Gb/s - 3.125 Gb/s TGJTT TLOCK TPHASE 960 1.061 Gb/s - 2.5 Gb/s < 1.06 Gb/s
TRCLK
80%
20%
TFCLK
DS083-3_01_120302
Figure 3: Reference Clock Timing Parameters
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Table 24: RocketIO X Receiver Switching Characteristics (1)
Description
Receive total jitter tolerance using default equalization and PRBS-15 pattern
Symbol
Conditions
2.488 Gb/s 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s 2.488 Gb/s 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s 2.488 Gb/s 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s 2.488 Gb/s 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s
Min
Typ
0.80 0.80 0.80 0.80 0.30 0.30 0.30 0.30 0.30 0.30 0.30 0.30 0.55 0.55 0.55 0.50 25
Max
0.65 0.65 0.65 0.65
Units
UI (2) UI UI UI UI UI UI UI
TJTOL
Receive random jitter tolerance
TRJTOL
0.15 0.15 0.15 0.15 0.45 0.45 0.45 0.45 34 (4) 55 55 250
UI UI UI UI UI UI UI UI RXUSRCLK cycles % % mV
Receive sinusoidal jitter tolerance measured at 70 MHz
TSJTOL
Receive deterministic jitter tolerance
TDJTOL
Receive
latency (3)
TRXLAT TRXDC TRX2DC VEYE 45 45
RXUSRCLK duty cycle RXUSRCLK2 duty cycle Differential receive input sensitivity
50 50 120
Notes: 1. The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate. 2. UI = Unit Interval
3. 4. Receive latency delay RXP/RXN to RXDATA. Refer to RocketIO X Transceiver User Guide for more information on calculating latency. This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both disabled, the maximum will be near the typical values.
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Table 25: RocketIO Receiver Switching Characteristics
Description Symbol Conditions
2.126 Gb/s - 3.125 Gb/s Receive total jitter tolerance TJTOL 1.0626 Gb/s - 2.125 Gb/s 1.0 Gb/s - 1.0625 Gb/s 600 Mb/s - 999 Mb/s 2.126 Gb/s - 3.125 Gb/s Receive deterministic jitter tolerance TDJTOL 1.0626 Gb/s - 2.125 Gb/s 1.0 Gb/s - 1.0625 Gb/s 600 Mb/s - 999 Mb/s Receive latency (3) RXUSRCLK duty cycle RXUSRCLK2 duty cycle Notes:
1. 2. 3. 4. UI = Unit Interval The oversampling techniques described in XAPP572 are required to meet these specifications for serial rates less than 1 Gb/s. Receive latency delay RXP/RXN to RXDATA. Refer to RocketIO Transceiver User Guide for more information on calculating latency. This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both disabled, the maximum will be near the typical values.
Min
Typ
Max
0.65 0.65 0.68 0.68(2) 0.41 0.43 0.47 0.47(2)
Units
UI (1) UI UI UI UI UI UI RXUSRCLK cycles % %
TRXLAT TRXDC TRX2DC 45 45
25 50 50
42 (4) 55 55
DATA ORIGINATES ..... 1 2
20
21
22
.....
820 821 822
.....
840 841 842
....
RXP/RXN TRXLAT RXDATA[16:0]
0 1 41 42 DATA ARRIVES
RXUSRCLK2
DS083-3_02_082301
Figure 4: RocketIO Receive Latency (Maximum)
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Table 26: RocketIO X Transmitter Switching Characteristics (1)
Description
Serial data rate
Symbol
FGTX
Conditions
BREFCLK Frequency
Min
2.488
Typ
Max
6.25
Units
Gb/s UI (2) UI UI UI UI UI UI UI UI UI UI UI ps ps
2.488 Gb/s Serial data output total jitter (p-p) (3) TTJ 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s 2.488 Gb/s Serial data output deterministic jitter (p-p) (3) TDJ 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s 2.488 Gb/s Serial data output random jitter (p-p) (3,4) TRJ 3.125 Gb/s 4.25 Gb/s 6.25 Gb/s TX rise time TX fall time Transmit latency (5) TXUSRCLK duty cycle TXUSRCLK2 duty cycle Notes:
1. 2. 3. 4. 5.
0.15 0.14 0.39 0.42 155.52 MHz 156.25 MHz 212.5 MHz 312.5 MHz 155.52 MHz 156.25 MHz 212.5 MHz 312.5 MHz 0.03 0.03 0.14 0.17 0.12 0.12 0.25 0.25 60 60 14 45 45 50 50
0.20 0.19 0.48 0.54 0.17 0.17 0.26 0.35 0.18 0.20 0.39 0.39
TRTX TFTX TTXLAT TTXDC TTX2DC
20% - 80% @ 2.500 Gb/s
19 55 55
TXUSR CLK cycles % %
The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate. UI = Unit Interval Total Jitter TTJ = TDJ + TRJ TRJ specifications are wideband and include low-frequency jitter components (also referred to as wander).TRJ specified is peak-to-peak, estimated at BER=10-12 using the Bathtub Method. Transmit latency delay TXDATA to TXP/TXN. Refer to RocketIO X Transceiver User Guide for more information on calculating latency.
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Table 27: RocketIO Transmitter Switching Characteristics
Description
Serial data rate, full-speed clock Serial data rate, half-speed clock(3) (2X oversampling) FGTX
Symbol
Conditions
Flipchip packages Wirebond packages Flipchip packages Wirebond packages 2.126 Gb/s - 3.125 Gb/s
Min
1.0 1.0 0.600 0.600
Typ
Max
3.125 (1) 2.5 (1) 1.0 1.0 0.17 0.08 0.05 0.08(4) 0.18 0.19 0.18 0.18(4)
Units
Gb/s Gb/s Gb/s Gb/s UI(2) UI UI UI UI UI UI UI ps ps
Serial data output deterministic jitter
TDJ
1.0626 Gb/s - 2.125 Gb/s 1.0 Gb/s - 1.0625 Gb/s 600 Mb/s - 999 Mb/s 2.126 Gb/s - 3.125 Gb/s
Serial data output random jitter
TRJ
1.0626 Gb/s - 2.125 Gb/s 1.0 Gb/s - 1.0625 Gb/s 600 Mb/s - 999 Mb/s
TX rise time TX fall time Transmit latency (5) TXUSRCLK duty cycle TXUSRCLK2 duty cycle Notes:
1. 2. 3. 4. 5.
TRTX TFTX TTXLAT TTXDC TTX2DC
20% - 80% Including CRC Excluding CRC 45 45
120 120 14 8 50 50 17 11 55 55
TXUSR CLK cycles % %
Serial data rate in the -5 speed grade is limited to 2.0 Gb/s in both wirebond and flipchip packages. UI = Unit Interval For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in XAPP572 are required to meet the transmit jitter and receive jitter tolerance specifications defined in this data sheet. The oversampling techniques described in XAPP572 are required to meet these specifications for serial rates less than 1 Gb/s. Transmit latency delay TXDATA to TXP/TXN. Refer to RocketIO Transceiver User Guide for more information on calculating latency.
1
2
.....
20
21
22
.....
320 321 322
.....
340 341 342
....
TXP/TXN TTXLAT
DATA ORIGINATES DATA ARRIVES
TXDATA[16:0]
0 1 16 17
TXUSRCLK2
DS083-3_03_082301
Figure 5: RocketIO Transmit Latency (Maximum, Including CRC)
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Table 28: RocketIO X Fabric Interface Characteristics
All Speed Grades Description
TX/RXUSRCLK frequency TX/RXUSRCLK2 frequency
Symbol
FTXRXUCLK FTXRXUCLK2
Min
125.00 62.50
Typ
Max
212.50 250.00
Units
MHz MHz
Table 29: RocketIO RXUSRCLK Switching Characteristics
Speed Grade Description
Setup and Hold Relative to Clock (RXUSRCLK) CHBONDI control inputs Clock to Out CHBONDO control outputs Clock RXUSRCLK minimum pulse width, High RXUSRCLK minimum pulse width, Low TGPWH_RX TGPWL_RX 2.83 2.83 2.83 2.83 4.50 4.50 ns, min ns, min TGCKCO_CHBO 0.50 0.50 0.55 ns, max TGCCK_CHBI/TGCKC_CHBI 0.00/ 0.12 0.00/ 0.12 0.00/ 0.14 ns, min
Symbol
-7
-6
-5
Units
Table 30: RocketIO RXUSRCLK2 Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (RXUSRCLK2) RXRESET control input RXPOLARITY control input ENCHANSYNC control input Clock to Out RXNOTINTABLE status outputs RXDISPERR status outputs RXCHARISCOMMA status outputs RXREALIGN status output RXCOMMADET status output RXLOSSOFSYNC status outputs RXCLKCORCNT status outputs RXBUFSTATUS status outputs RXCHECKINGCRC status output RXCRCERR status output CHBONDDONE status output RXCHARISK status outputs RXRUNDISP status outputs RXDATA data outputs TGCKST_RNIT TGCKST_RDERR TGCKST_RCMCH TGCKST_ALIGN TGCKST_CMDT TGCKST_RLOS TGCKST_RCCCNT TGCKST_RBSTA TGCKST_RCCRC TGCKST_RCRCE TGCKST_CHBD TGCKST_RKCH TGCKST_RRDIS TGCKDO_RDAT 0.50 0.50 0.50 0.41 0.41 0.50 0.41 0.45 0.36 0.36 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.41 0.41 0.50 0.41 0.45 0.40 0.40 0.50 0.50 0.50 0.50 0.55 0.55 0.55 0.46 0.46 0.55 0.46 0.50 0.44 0.44 0.55 0.55 0.55 0.55 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
TGCCK_RRST/TGCKC_RRST TGCCK_RPOL/TGCKC_RPOL TGCCK_ECSY/TGCKC_ECSY
Symbol
-7
-6
-5
Units
0.02/ 0.00 0.02/ 0.00 0.02/ 0.00
0.02/ 0.00 0.02/ 0.00 0.02/ 0.00
0.02/ 0.00 0.02/ 0.00 0.02/ 0.00
ns, min ns, min ns, min
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Table 30: RocketIO RXUSRCLK2 Switching Characteristics (Continued) Speed Grade Description
Clock RXUSRCLK2 minimum pulse width, High RXUSRCLK2 minimum pulse width, Low TGPWH_RX2 TGPWL_RX2 1.42 1.42 1.42 1.42 2.25 2.25 ns, min ns, min
Symbol
-7
-6
-5
Units
Table 31: RocketIO TXUSRCLK2 Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (TXUSRCLK2) CONFIGENABLE control input TXBYPASS8B10B control inputs TXFORCECRCERR control input TXPOLARITY control input TXINHIBIT control inputs LOOPBACK control inputs TXRESET control input TXCHARISK control inputs TXCHARDISPMODE control inputs TXCHARDISPVAL control inputs CONFIGIN data input TXDATA data inputs Clock to Out TXBUFERR status output TXKERR status outputs TXRUNDISP status outputs CONFIGOUT data output Clock TXUSRCLK2 minimum pulse width, High TXUSRCLK2 minimum pulse width, Low TGPWH_TX2 TGPWL_TX2 1.42 1.42 1.42 1.42 2.25 2.25 ns, min ns, min TGCKST_TBERR TGCKST_TKERR TGCKST_TRDIS TGCKDO_CFGOUT 0.54 0.41 0.41 0.25 0.54 0.41 0.41 0.25 0.60 0.46 0.46 0.28 ns, max ns, max ns, max ns, max TGCCK_CFGEN/TGCKC_CFGEN TGCCK_TBYP/TGCKC_TBYP TGCCK_TCRCE/TGCKC_TCRCE TGCCK_TPOL/TGCKC_TPOL TGCCK_TINH/TGCKC_TINH TGCCK_LBK/TGCKC_LBK TGCCK_TRST/TGCKC_TRST TGCCK_TKCH/TGCKC_TKCH TGCCK_TCDM/TGCKC_TCDM TGCCK_TCDV/TGCKC_TCDV TGDCK_CFGIN/TGCKD_CFGIN TGDCK_TDAT/TGCKD_TDAT 0.35/ 0.10 0.02/ 0.00 0.39/ 0.12 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.02/ 0.10 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.35/ 0.10 0.02/ 0.00 0.35/ 0.10 0.02/ 0.00 0.44/ 0.14 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.02/ 0.10 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.35/ 0.10 0.02/ 0.00 0.39/ 0.11 0.02/ 0.00 0.49/ 0.15 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.02/ 0.11 0.02/ 0.00 0.02/ 0.00 0.02/ 0.00 0.39/ 0.11 0.02/ 0.00 ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min
Symbol
-7
-6
-5
Units
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVCMOS 2.5V levels. For other standards, adjust the delays with the values shown in IOB Input Switching Characteristics Standard Adjustments. Table 32: IOB Input Switching Characteristics Speed Grade Description
Propagation Delays Pad to I output, no delay Pad to I output, with delay TIOPI TIOPID All XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Propagation Delays Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay TIOPLI TIOPLID All XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Clock CLK to output IQ TIOCKIQ All 0.86 2.30 2.57 2.50 2.65 2.65 2.69 3.30 3.86 4.00 4.00 N/A 0.60 0.89 2.62 2.89 2.84 3.04 3.04 3.12 3.63 4.10 4.25 4.25 6.50 0.60 0.93 2.97 3.23 3.17 3.42 3.42 3.51 4.03 4.45 4.57 4.57 7.06 0.67 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max 0.84 1.84 1.84 1.84 2.14 2.14 2.14 2.54 2.54 2.54 2.54 N/A 0.87 1.94 1.94 1.94 2.23 2.23 2.26 2.67 2.68 2.72 2.72 4.71 0.91 2.06 2.06 2.06 2.37 2.37 2.46 2.81 2.87 2.91 2.91 4.80 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Symbol
Device
-7
-6
-5
Units
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Table 32: IOB Input Switching Characteristics (Continued) Speed Grade Description
Setup and Hold Times With Respect to Clock at IOB Input Register Pad, no delay Pad, with delay TIOPICK/TIOICKP TIOPICKD/TIOICKPD All XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 ICE input SR input (IFF, synchronous) Set/Reset Delays SR input to IQ (asynchronous) GSR to output IQ TIOSRIQ TGSRQ All All 1.13 5.87 1.27 6.75 1.42 7.43 ns, max ns, max TIOICECK/TIOCKICE TIOSRCKI All All 0.84/-0.61 2.28/-1.89 2.55/-2.10 2.48/-2.05 2.63/-2.05 2.63/-2.05 2.67/-2.07 3.28/-2.56 3.84/-3.02 3.98/-3.13 3.98/-3.13 N/A 0.39/ 0.01 0.52 0.86/-0.63 2.60/-2.15 2.87/-2.36 2.82/-2.32 3.02/-2.35 3.02/-2.35 3.09/-2.42 3.61/-2.83 4.08/-3.21 4.23/-3.33 4.23/-3.33 6.48/-5.13 0.44/ 0.01 0.57 0.90/-0.67 2.95/-2.43 3.21/-2.65 3.15/-2.60 3.40/-2.66 3.40/-2.66 3.49/-2.73 4.01/-3.15 4.42/-3.48 4.55/-3.58 4.55/-3.58 7.04/-5.57 0.49/ 0.01 0.75 ns, min ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, min ns, min
Symbol
Device
-7
-6
-5
Units
Notes: 1. Input timing for LVCMOS25 is measured at 1.25V. For other I/O standards, see Table 36.
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IOB Input Switching Characteristics Standard Adjustments
Table 33 gives all standard-specific data input delay adjustments. Table 33: IOB Input Switching Characteristics Standard Adjustments
IOSTANDARD Attribute
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVDS_25 LVDSEXT_25 ULVDS_25 BLVDS_25 LDT_25 LVPECL_25 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III_18 HSTL_IV_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 HSLVDCI_15
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V ULVDS (Ultra LVDS), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI, 2.5V LVDCI, 1.8V LVDCI, 1.5V LVDCI, 2.5V, Half-Impedance LVDCI, 1.8V, Half-Impedance LVDCI, 1.5V, Half-Impedance HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
Timing Parameter
TILVTTL TILVCMOS33 TILVCMOS25 TILVCMOS18 TILVCMOS15 TILVDS_25
Speed Grade -7
0.07 0.04 0.00 0.29 0.36 0.31 0.33 0.31 0.00 0.31 0.69 0.14 0.15 0.12 0.59 0.63 0.59 0.59 0.57 0.58 0.57 0.55 0.56 0.57 0.62 0.64 0.62 0.64 -0.05 0.00 0.07 0.13 0.00 0.07 0.13 0.59
-6
0.08 0.05 0.00 0.33 0.41 0.36 0.37 0.36 0.00 0.36 0.80 0.16 0.17 0.13 0.68 0.72 0.68 0.68 0.66 0.67 0.65 0.63 0.64 0.65 0.72 0.73 0.72 0.73 -0.05 0.00 0.09 0.15 0.00 0.09 0.15 0.68
-5
0.09 0.05 0.00 0.36 0.45 0.40 0.41 0.40 0.00 0.40 0.88 0.18 0.19 0.15 0.74 0.79 0.75 0.75 0.72 0.74 0.72 0.69 0.70 0.71 0.79 0.81 0.79 0.81 -0.06 0.00 0.09 0.17 0.00 0.09 0.17 0.75
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TILVDSEXT_25 TIULVDS_25 TIBLVDS_25 TILDT_25 TILVPECL_25
TIPCI33_3 TIPCI66_3 TIPCIX TIGTL TIGTLP TIHSTL_I TIHSTL_II TIHSTL_III TIHSTL_IV TIHSTL_I_18 TIHSTL_II_18 TIHSTL_III_18 TIHSTL_IV_18
TISSTL18_I TISSTL18_II
TISSTL2_I TISSTL2_II TILVDCI_33 TILVDCI_25 TILVDCI_18 TILVDCI_15 TILVDCI_DV2_25 TILVDCI_DV2_18 TILVDCI_DV2_15 TIHSLVDCI_15
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Table 33: IOB Input Switching Characteristics Standard Adjustments (Continued)
IOSTANDARD Attribute
HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL18_I_DCI SSTL18_II_DCI SSTL2_I_DCI SSTL2_II_DCI LVDS_25_DCI LVDSEXT_25_DCI LVDS_25_DT LVDSEXT_25_DT ULVDS_25_DT LDT_25_DT
Description
HSLVDCI, 1.8V HSLVDCI, 2.5V HSLVDCI, 3.3V GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI HSTL (High-Speed Transceiver Logic), Class I, with DCI HSTL, Class II, with DCI HSTL, Class III, with DCI HSTL, Class IV, with DCI HSTL, Class I, 1.8V, with DCI HSTL, Class II, 1.8V, with DCI HSTL, Class III, 1.8V, with DCI HSTL, Class IV, 1.8V, with DCI SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI SSTL, Class II, 1.8V, with DCI SSTL, Class I, 2.5V, with DCI SSTL, Class II, 2.5V, with DCI LVDS, 2.5V, with DCI LVDSEXT, 2.5V, with DCI LVDS, 2.5V, with Differential Termination (DT) LVDSEXT, 2.5V, with DT ULVDS, 2.5V, with DT LDT, 2.5V, with DT
Timing Parameter
TIHSLVDCI_18 TIHSLVDCI_25 TIHSLVDCI_33 TIGTL_DCI TIGTLP_DCI TIHSTL_I_DCI TIHSTL_II_DCI TIHSTL_III_DCI TIHSTL_IV_DCI TIHSTL_I_DCI_18 TIHSTL_II_DCI_18 TIHSTL_III_DCI_18 TIHSTL_IV_DCI_18
Speed Grade -7
0.59 0.59 0.59 0.49 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.62 0.64 0.17 0.17 0.31 0.33 0.31 0.33 0.31 0.31
-6
0.68 0.68 0.68 0.57 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.72 0.73 0.20 0.20 0.36 0.37 0.36 0.37 0.36 0.36
-5
0.75 0.75 0.75 0.62 0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.79 0.81 0.22 0.22 0.40 0.41 0.40 0.41 0.40 0.40
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TISSTL18_I_DCI TISSTL18_II_DCI
TISSTL2_I_DCI TISSTL2_II_DCI
TILVDS_25_DCI TILVDSEXT_25_DCI
TILVDS_25_DT
TILVDSEXT_25_DT TIULVDS_25_DT TILDT_25_DT
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IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments. Table 34: IOB Output Switching Characteristics
Speed Grade Description
Propagation Delays O input to Pad O input to Pad via transparent latch 3-State Delays T input to Pad high-impedance (2) T input to valid data on Pad T input to Pad high-impedance via transparent latch (2) T input to valid data on Pad via transparent latch GTS to Pad high-impedance (2) Sequential Delays Clock CLK to Pad Clock CLK to Pad high-impedance (synchronous) (2) Clock CLK to valid data on Pad (synchronous) Setup and Hold Times Before/After Clock CLK O input OCE input SR input (OFF) 3-State Setup Times, T input 3-State Setup Times, TCE input 3-State Setup Times, SR input (TFF) Set/Reset Delays Minimum Pulse Width, SR inputs (asynchronous) SR input to Pad (asynchronous) SR input to Pad high-impedance (asynchronous) (2) SR input to valid data on Pad (asynchronous) GSR to Pad TRPW TIOSRP TIOSRHZ TIOSRON TIOGSRQ 0.37 2.33 1.97 2.24 5.87 0.40 2.56 2.16 2.44 6.75 0.45 2.83 2.41 2.69 7.43 ns, min ns, max ns, max ns, max ns, max TIOOCK/TIOCKO TIOOCECK/TIOCKOCE TIOSRCKO/TIOCKOSR TIOTCK/TIOCKT TIOTCECK/TIOCKTCE TIOSRCKT/TIOCKTSR 0.23/ 0.12 0.39/ 0.01 0.52/ 0.00 0.23/ 0.12 0.39/ 0.01 0.52/ 0.00 0.26/ 0.14 0.44/ 0.01 0.57/ 0.00 0.26/ 0.14 0.44/ 0.01 0.57/ 0.00 0.29/ 0.15 0.49/ 0.01 0.75/ 0.00 0.29/ 0.15 0.49/ 0.01 0.75/ 0.00 ns, min ns, min ns, min ns, min ns, min ns, min TIOCKP TIOCKHZ TIOCKON 1.59 1.39 1.67 1.76 1.55 1.82 1.93 1.73 2.00 ns, max ns, max ns, max TIOTHZ TIOTP TIOTLPHZ TIOTLPON TGTS 1.23 1.51 1.08 1.56 4.11 1.35 1.63 1.22 1.69 4.73 1.51 1.78 1.36 1.85 5.20 ns, max ns, max ns, max ns, max ns, max TIOOP TIOOLP 1.58 1.65 1.68 1.82 1.85 1.99 ns, max ns, max
Symbol
-7
-6
-5
Units
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. The 3-state turn-off delays should not be adjusted.
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IOB Output Switching Characteristics Standard Adjustments
Table 35 gives all standard-specific adjustments for output delays terminating at pads, based on standard capacitive load, CREF. Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 35: IOB Output Switching Characteristics Standard Adjustments
Description
LVTTL (Low-Voltage Transistor-Transistor Logic), Slow, 2 mA LVTTL, Slow, 4 mA LVTTL, Slow, 6 mA LVTTL, Slow, 8 mA LVTTL, Slow, 12 mA LVTTL, Slow, 16 mA LVTTL, Slow, 24 mA LVTTL, Fast, 2 mA LVTTL, Fast, 4 mA LVTTL, Fast, 6 mA LVTTL, Fast, 8 mA LVTTL, Fast, 12 mA LVTTL, Fast, 16 mA LVTTL, Fast, 24 mA LVCMOS (Low-Voltage CMOS), 3.3V, Slow, 2 mA LVCMOS, 3.3V, Slow, 4 mA LVCMOS, 3.3V, Slow, 6 mA LVCMOS, 3.3V, Slow, 8 mA LVCMOS, 3.3V, Slow, 12 mA LVCMOS, 3.3V, Slow, 16 mA LVCMOS, 3.3V, Slow, 24 mA LVCMOS, 3.3V, Fast, 2 mA LVCMOS, 3.3V, Fast, 4 mA LVCMOS, 3.3V, Fast, 6 mA LVCMOS, 3.3V, Fast, 8 mA LVCMOS, 3.3V, Fast, 12 mA LVCMOS, 3.3V, Fast, 16 mA LVCMOS, 3.3V, Fast, 24 mA LVCMOS, 2.5V, Slow, 2 mA LVCMOS, 2.5V, Slow, 4 mA LVCMOS, 2.5V, Slow, 6 mA LVCMOS, 2.5V, Slow, 8 mA LVCMOS, 2.5V, Slow, 12 mA LVCMOS, 2.5V, Slow, 16 mA LVCMOS, 2.5V, Slow, 24 mA LVCMOS, 2.5V, Fast, 2 mA LVCMOS, 2.5V, Fast, 4 mA
IOSTANDARD Attribute
LVTTL_S2 LVTTL_S4 LVTTL_S6 LVTTL_S8 LVTTL_S12 LVTTL_S16 LVTTL_S24 LVTTL_F2 LVTTL_F4 LVTTL_F6 LVTTL_F8 LVTTL_F12 LVTTL_F16 LVTTL_F24 LVCMOS33_S2 LVCMOS33_S4 LVCMOS33_S6 LVCMOS33_S8 LVCMOS33_S12 LVCMOS33_S16 LVCMOS33_S24 LVCMOS33_F2 LVCMOS33_F4 LVCMOS33_F6 LVCMOS33_F8 LVCMOS33_F12 LVCMOS33_F16 LVCMOS33_F24 LVCMOS25_S2 LVCMOS25_S4 LVCMOS25_S6 LVCMOS25_S8 LVCMOS25_S12 LVCMOS25_S16 LVCMOS25_S24 LVCMOS25_F2 LVCMOS25_F4
Timing Parameter
TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 TOLVTTL_S8 TOLVTTL_S12 TOLVTTL_S16 TOLVTTL_S24 TOLVTTL_F2 TOLVTTL_F4 TOLVTTL_F6 TOLVTTL_F8 TOLVTTL_F12 TOLVTTL_F16 TOLVTTL_F24 TOLVCMOS33_S2 TOLVCMOS33_S4 TOLVCMOS33_S6 TOLVCMOS33_S8 TOLVCMOS33_S12 TOLVCMOS33_S16 TOLVCMOS33_S24 TOLVCMOS33_F2 TOLVCMOS33_F4 TOLVCMOS33_F6 TOLVCMOS33_F8 TOLVCMOS33_F12 TOLVCMOS33_F16 TOLVCMOS33_F24 TOLVCMOS25_S2 TOLVCMOS25_S4 TOLVCMOS25_S6 TOLVCMOS25_S8 TOLVCMOS25_S12 TOLVCMOS25_S16 TOLVCMOS25_S24 TOLVCMOS25_F2 TOLVCMOS25_F4
Speed Grade -7
5.42 3.09 2.26 1.47 1.02 0.46 0.37 4.42 1.95 1.10 0.40 0.24 0.05 -0.01 5.42 3.14 2.26 1.47 1.03 0.45 0.39 4.46 1.96 1.11 0.41 0.23 0.02 -0.07 4.12 2.43 1.76 1.04 0.76 0.41 0.23 3.29 1.31
-6
6.24 3.55 2.60 1.69 1.18 0.53 0.42 5.09 2.24 1.26 0.46 0.27 0.06 -0.01 6.23 3.61 2.60 1.69 1.18 0.52 0.44 5.13 2.25 1.28 0.47 0.26 0.02 -0.08 4.74 2.80 2.02 1.19 0.87 0.47 0.26 3.78 1.50
-5
6.86 3.91 2.86 1.86 1.29 0.58 0.47 5.59 2.46 1.39 0.51 0.30 0.07 -0.01 6.86 3.97 2.86 1.86 1.30 0.57 0.49 5.64 2.48 1.40 0.52 0.28 0.03 -0.09 5.21 3.07 2.22 1.31 0.96 0.52 0.28 4.16 1.65
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
LVCMOS, 2.5V, Fast, 6 mA LVCMOS, 2.5V, Fast, 8 mA LVCMOS, 2.5V, Fast, 12 mA LVCMOS, 2.5V, Fast, 16 mA LVCMOS, 2.5V, Fast, 24 mA LVCMOS, 1.8V, Slow, 2 mA LVCMOS, 1.8V, Slow, 4 mA LVCMOS, 1.8V, Slow, 6 mA LVCMOS, 1.8V, Slow, 8 mA LVCMOS, 1.8V, Slow, 12 mA LVCMOS, 1.8V, Slow, 16 mA LVCMOS, 1.8V, Fast, 2 mA LVCMOS, 1.8V, Fast, 4 mA LVCMOS, 1.8V, Fast, 6 mA LVCMOS, 1.8V, Fast, 8 mA LVCMOS, 1.8V, Fast, 12 mA LVCMOS, 1.8V, Fast, 16 mA LVCMOS, 1.5V, Slow, 2 mA LVCMOS, 1.5V, Slow, 4 mA LVCMOS, 1.5V, Slow, 6 mA LVCMOS, 1.5V, Slow, 8 mA LVCMOS, 1.5V, Slow, 12 mA LVCMOS, 1.5V, Slow, 16 mA LVCMOS, 1.5V, Fast, 2 mA LVCMOS, 1.5V, Fast, 4 mA LVCMOS, 1.5V, Fast, 6 mA LVCMOS, 1.5V, Fast, 8 mA LVCMOS, 1.5V, Fast, 12 mA LVCMOS, 1.5V, Fast, 16 mA LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V ULVDS (Ultra LVDS), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I
IOSTANDARD Attribute
LVCMOS25_F6 LVCMOS25_F8 LVCMOS25_F12 LVCMOS25_F16 LVCMOS25_F24 LVCMOS18_S2 LVCMOS18_S4 LVCMOS18_S6 LVCMOS18_S8 LVCMOS18_S12 LVCMOS18_S16 LVCMOS18_F2 LVCMOS18_F4 LVCMOS18_F6 LVCMOS18_F8 LVCMOS18_F12 LVCMOS18_F16 LVCMOS15_S2 LVCMOS15_S4 LVCMOS15_S6 LVCMOS15_S8 LVCMOS15_S12 LVCMOS15_S16 LVCMOS15_F2 LVCMOS15_F4 LVCMOS15_F6 LVCMOS15_F8 LVCMOS15_F12 LVCMOS15_F16 LVDS_25 LVDSEXT_25 ULVDS_25 BLVDS_25 LDT_25 LVPECL_25 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I
Timing Parameter
TOLVCMOS25_F6 TOLVCMOS25_F8 TOLVCMOS25_F12 TOLVCMOS25_F16 TOLVCMOS25_F24 TOLVCMOS18_S2 TOLVCMOS18_S4 TOLVCMOS18_S6 TOLVCMOS18_S8 TOLVCMOS18_S12 TOLVCMOS18_S16 TOLVCMOS18_F2 TOLVCMOS18_F4 TOLVCMOS18_F6 TOLVCMOS18_F8 TOLVCMOS18_F12 TOLVCMOS18_F16 TOLVCMOS15_S2 TOLVCMOS15_S4 TOLVCMOS15_S6 TOLVCMOS15_S8 TOLVCMOS15_S12 TOLVCMOS15_S16 TOLVCMOS15_F2 TOLVCMOS15_F4 TOLVCMOS15_F6 TOLVCMOS15_F8 TOLVCMOS15_F12 TOLVCMOS15_F16 TOLVDS_25 TOLVDSEXT_25 TOULVDS_25 TOBLVDS_25 TOLDT_25 TOLVPECL_25 TOPCI33_3 TOPCI66_3 TOPCIX TOGTL TOGTLP TOHSTL_I
Speed Grade -7
0.62 0.20 0.00 -0.03 -0.15 4.20 2.76 1.91 1.92 1.58 0.76 2.34 0.71 0.50 0.48 0.30 0.11 6.19 4.28 2.81 2.55 1.31 1.28 2.26 1.66 0.65 0.94 0.25 0.28 0.01 0.13 0.13 0.00 0.13 0.17 0.83 0.89 0.92 0.08 0.04 0.56
-6
0.71 0.23 0.00 -0.03 -0.15 4.83 3.18 2.20 2.20 1.81 0.87 2.69 0.81 0.57 0.55 0.34 0.12 7.12 4.93 3.24 2.93 1.51 1.47 2.60 1.90 0.75 1.08 0.29 0.32 0.01 0.15 0.14 0.00 0.14 0.19 0.93 0.97 1.02 0.10 0.05 0.64
-5
0.78 0.25 0.00 -0.04 -0.15 5.31 3.49 2.41 2.42 1.99 0.96 2.95 0.89 0.63 0.61 0.38 0.13 7.83 5.42 3.56 3.23 1.66 1.62 2.86 2.09 0.82 1.19 0.32 0.35 0.01 0.16 0.16 0.00 0.16 0.21 1.01 1.05 1.10 0.11 0.06 0.70
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI, 2.5V LVDCI, 1.8V LVDCI, 1.5V LVDCI, 2.5V, Half-Impedance LVDCI, 1.8V, Half-Impedance LVDCI, 1.5V, Half-Impedance HSLVDCI (High-Speed Low-Voltage DCI), 1.5V HSLVDCI, 1.8V HSLVDCI, 2.5V HSLVDCI, 3.3V GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI HSTL (High-Speed Transceiver Logic), Class I, with DCI HSTL, Class II, with DCI HSTL, Class III, with DCI HSTL, Class IV, with DCI HSTL, Class I, 1.8V, with DCI HSTL, Class II, 1.8V, with DCI HSTL, Class III, 1.8V, with DCI HSTL, Class IV, 1.8V, with DCI SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI SSTL, Class II, 1.8V, with DCI SSTL, Class I, 2.5V, with DCI SSTL, Class II, 2.5V, with DCI
IOSTANDARD Attribute
HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III_18 HSTL_IV_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL18_I_DCI SSTL18_II_DCI SSTL2_I_DCI SSTL2_II_DCI
Timing Parameter
TOHSTL_II TOHSTL_IIII TOHSTL_IV TOHSTL_I_18 TOHSTL_II_18 TOHSTL_IIII_18 TOHSTL_IV_18 TOSSTL18_I TOSSTL18_II TOSSTL2_I TOSSTL2_II TOLVDCI_33 TOLVDCI_25 TOLVDCI_18 TOLVDCI_15 TOLVDCI_DV2_25 TOLVDCI_DV2_18 TOLVDCI_DV2_15 TOHSLVDCI_15 TOHSLVDCI_18 TOHSLVDCI_25 TOHSLVDCI_33 TOGTL_DCI TOGTLP_DCI TOHSTL_I_DCI TOHSTL_II_DCI TOHSTL_III_DCI TOHSTL_IV_DCI TOHSTL_I_DCI_18 TOHSTL_II_DCI_18 TOHSTL_III_DCI_18 TOHSTL_IV_DCI_18 TOSSTL18_I_DCI TOSSTL18_II_DCI TOSSTL2_I_DCI TOSSTL2_II_DCI
Speed Grade -7
0.30 0.31 0.15 0.56 0.30 0.36 0.19 0.80 0.45 0.63 0.22 0.72 0.56 0.65 1.00 0.06 0.30 0.60 1.00 0.65 0.56 0.72 1.21 0.05 0.55 0.47 0.31 1.81 0.55 0.24 0.35 1.48 0.54 0.24 0.48 0.48
-6
0.35 0.35 0.17 0.64 0.35 0.41 0.22 0.92 0.51 0.72 0.25 0.83 0.64 0.75 1.15 0.07 0.34 0.69 1.15 0.75 0.64 0.83 1.39 0.06 0.63 0.54 0.36 2.08 0.63 0.28 0.40 1.70 0.62 0.28 0.56 0.56
-5
0.38 0.39 0.19 0.70 0.38 0.45 0.24 1.01 0.56 0.79 0.27 0.91 0.71 0.82 1.26 0.08 0.38 0.76 1.26 0.82 0.71 0.91 1.53 0.07 0.69 0.60 0.40 2.29 0.70 0.31 0.44 1.87 0.68 0.31 0.61 0.61
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 36 shows the test setup parameters used for measuring Input standard adjustments (see Table 33, page 23). Table 36: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III & IV HSTL, Class I & II, 1.8V HSTL, Class III & IV, 1.8V SSTL (Stub Terminated Tnscvr Logic), Class I & II, 2.5V SSTL, Class I & II, 1.8V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V ULVDS (Ultra LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V
IOSTANDARD Attribute
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I, HSTL_II HSTL_III, HSTL_IV HSTL_I_18, HSTL_II_18 HSTL_III_18, HSTL_IV_18 SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II LVDS_25 LVDSEXT_25 ULVDS_25 LDT_25 LVPECL_25
VL (1,2)
0 0 0 0 0
VH (1,2)
3.3 3.3 2.5 1.8 1.5
VMEAS
(1,4,5)
VREF
(1,3,5)
1.65 1.65 1.25 0.9 0.75
- - - - - - - -
Per PCI Specification Per PCI Specification Per PCI-X Specification VREF - 0.2 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.75 VREF - 0.5 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125 0.6 - 0.125 1.15 - 0.3 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.75 VREF + 0.5 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 0.6 + 0.125 1.15 + 0.3 VREF VREF VREF VREF VREF VREF VREF VREF 1.2 1.2 0.6 0.6 1.15
0.80 1.0 0.75 0.90 0.90 1.08 1.25 0.9
Notes:
1. 2. 3. 4. 5. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same as for the corresponding non-DCI standards. Input waveform switches between VLand VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. See Virtex-II Pro Platform FPGA User Guide for min/max specifications. Input voltage level from which measurement starts. Note that this is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Output Standard Adjustment value (Table 35) to yield the actual worst-case propagation delay (clock-to-input) of the PCB trace.
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. (See Virtex-II Pro Platform FPGA User Guide for details.) The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown in Figure 6. Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. (IBIS models can be found on the web at http://support.xilinx.com/support/sw_ibis.htm.) Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 37. 2. Record the time to VMEAS . 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. Table 37: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V
VREF FPGA Output
RREF
VMEAS (voltage level at which delay measurement is taken) CREF
(probe capacitance)
ds083-3_06a_092503
Figure 6: Generalized Test Setup
IOSTANDARD Attribute LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 (rising edge) PCI33_3 (falling edge) PCI66_3 (rising edge) PCI66_3 (falling edge) PCIX (rising edge) PCIX (falling edge GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III_18 HSTL_IV_18
RREF () 1M 1M 1M 1M 1M 25 25 25 25 25 25 25 25 50 25 50 25 50 25 50 25
CREF(1) (pF) 0 0 0 0 0 10 (2) 10 (2) 10 (2) 10 (2) 10 (3) 10 (3) 0 0 0 0 0 0 0 0 0 0
VMEAS (V) 1.65 1.65 1.25 0.9 0.75 0.94 2.03 0.94 2.03 0.94 2.03 0.8 1.0 VREF VREF 0.9 0.9 VREF VREF 1.1 1.1
VREF (V) 0 0 0 0 0 0 3.3 0 3.3 0 3.3 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V
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Table 37: Output Delay Measurement Methodology
Description
SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL, Class III & IV, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III & IV, 1.8V, with DCI SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL, Class I & II, 2.5V, with DCI GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI
IOSTANDARD Attribute SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDSEXT_25 BLVDS_25 LDT_25 LVPECL_25 LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 HSTL_I_DCI, HSTL_II_DCI HSTL_III_DCI, HSTL_IV_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18, HSTL_IV_DCI_18 SSTL18_I_DCI, SSTL18_II_DCI SSTL2_I_DCI, SSTL2_II_DCI GTL_DCI GTLP_DCI
RREF () 50 25 50 25 50 50 1M 50 1M 1M 1M 1M 1M 50 50 50 50 50 50 50 50
CREF(1) (pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VMEAS (V) VREF VREF VREF VREF VREF VREF 1.2 VREF 1.23 1.65 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF 0.8 1.0
VREF (V) 0.9 0.9 1.25 1.25 1.2 1.2 0 0.6 0 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25 1.2 1.5
Notes:
1. 2. 3. CREF is the capacitance of the probe, nominally 0 pF. Measured as per PCI specification. Measured as per PCI-X specification.
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Clock Distribution Switching Characteristics
Table 38: Clock Distribution Switching Characteristics Speed Grade Description
Global Clock Buffer I input to O output Global Clock Buffer S input Setup/Hold to I1 an I2 inputs
Symbol
TGIO TGSI/TGIS
-7 0.05 0.49/-0.10
-6 0.057 0.54/-0.12
-5 0.064 0.60/-0.13
Units
ns, max ns, max
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 34 in Module 2). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 39: CLB Switching Characteristics Speed Grade Description
Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output FXINA or FXINB inputs to Y output via MUXFX FXINA input to FX output via MUXFX FXINB input to FX output via MUXFX SOPIN input to SOPOUT output via ORCY Incremental delay routing through transparent latch to XQ/YQ outputs Sequential Delays FF Clock CLK to XQ/YQ outputs Latch Clock CLK to XQ/YQ outputs Setup and Hold Times Before/After Clock CLK BX/BY inputs DY inputs DX inputs CE input SR/BY inputs (synchronous) Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Set/Reset Minimum Pulse Width, SR/BY inputs (asynchronous) Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Toggle Frequency (for export control) TRPW TRQ FTOG 0.37 1.09 1350 0.40 1.25 1200 0.45 1.40 1050 ns, min ns, max MHz TCH TCL 0.37 0.37 0.40 0.40 0.45 0.45 ns, min ns, min TDICK/TCKDI TDYCK/TCKDY TDXCK/TCKDX TCECK/TCKCE TRCK/TCKR 0.21/-0.04 0.00/ 0.12 0.00/ 0.12 0.27/ 0.01 0.55/-0.01 0.24/-0.05 0.00/ 0.14 0.00/ 0.14 0.34/ 0.01 0.60/-0.01 0.27/-0.06 0.00/ 0.15 0.00/ 0.15 0.47/ 0.01 0.78/-0.01 ns, min ns, min ns, min ns, min ns, min TCKO TCKLO 0.37 0.54 0.38 0.57 0.42 0.64 ns, max ns, max TILO TIF5 TIF5X TIFXY TINAFX TINBFX TSOPSOP TIFNCTL 0.28 0.59 0.63 0.29 0.29 0.29 0.11 0.23 0.32 0.65 0.70 0.32 0.32 0.32 0.13 0.24 0.36 0.73 0.79 0.36 0.36 0.36 0.14 0.27 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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CLB Distributed RAM Switching Characteristics
Table 40: CLB Distributed RAM Switching Characteristics Speed Grade Description
Sequential Delays Clock CLK to X/Y outputs (WE active) in 16 x 1 mode Clock CLK to X/Y outputs (WE active) in 32 x 1 mode Clock CLK to F5 output Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) F/G address inputs SR input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time TWPH TWPL TWC 0.63 0.63 1.25 0.72 0.72 1.44 0.79 0.79 1.58 ns, min ns, min ns, min TDS/TDH TAS/TAH TWES/TWEH 0.38/-0.07 0.42/ 0.00 0.22/ 0.04 0.41/-0.07 0.47/ 0.00 0.24/ 0.05 0.46/-0.08 0.52/ 0.00 0.26/ 0.05 ns, min ns, min ns, min TSHCKO16 TSHCKO32 TSHCKOF5 1.25 1.57 1.52 1.38 1.75 1.68 1.54 1.95 1.88 ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
CLB Shift Register Switching Characteristics
Table 41: CLB Shift Register Switching Characteristics Speed Grade Description
Sequential Delays Clock CLK to X/Y outputs Clock CLK to X/Y outputs Clock CLK to XB output via MC15 LUT output Clock CLK to YB output via MC15 LUT output Clock CLK to Shiftout Clock CLK to F5 output Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) SR input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low TSRPH TSRPL 0.63 0.63 0.72 0.72 0.79 0.79 ns, min ns, min TSRLDS/TSRLDH TWSS/TWSH 0.70/-0.16 0.27/ 0.01 0.77/-0.18 0.34/ 0.01 0.98/-0.21 0.47/ 0.01 ns, min ns, min TREG TREG32 TREGXB TREGYB TCKSH TREGF5 2.78 3.10 2.84 2.55 2.50 3.05 3.12 3.49 3.18 2.88 2.83 3.42 3.49 3.90 3.55 3.21 3.15 3.83 ns, max ns, max ns, max ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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Multiplier Switching Characteristics
Table 42: Multiplier Switching Characteristics Speed Grade Description Propagation Delay to Output Pin
Input to Pin35 Input to Pin34 Input to Pin33 Input to Pin32 Input to Pin31 Input to Pin30 Input to Pin29 Input to Pin28 Input to Pin27 Input to Pin26 Input to Pin25 Input to Pin24 Input to Pin23 Input to Pin22 Input to Pin21 Input to Pin20 Input to Pin19 Input to Pin18 Input to Pin17 Input to Pin16 Input to Pin15 Input to Pin14 Input to Pin13 Input to Pin12 Input to Pin11 Input to Pin10 Input to Pin9 Input to Pin8 Input to Pin7 Input to Pin6 Input to Pin5 Input to Pin4 Input to Pin3 Input to Pin2 Input to Pin1 Input to Pin0 TMULT_P35 TMULT_P34 TMULT_P33 TMULT_P32 TMULT_P31 TMULT_P30 TMULT_P29 TMULT_P28 TMULT_P27 TMULT_P26 TMULT_P25 TMULT_P24 TMULT_P23 TMULT_P22 TMULT_P21 TMULT_P20 TMULT_P19 TMULT_P18 TMULT_P17 TMULT_P16 TMULT_P15 TMULT_P14 TMULT_P13 TMULT_P12 TMULT_P11 TMULT_P10 TMULT_P9 TMULT_P8 TMULT_P7 TMULT_P6 TMULT_P5 TMULT_P4 TMULT_P3 TMULT_P2 TMULT_P1 TMULT_P0 4.08 3.99 3.90 3.80 3.71 3.62 3.53 3.43 3.34 3.25 3.16 3.06 2.97 2.88 2.79 2.70 2.60 2.51 2.42 2.34 2.27 2.19 2.12 2.04 1.96 1.89 1.81 1.74 1.66 1.59 1.51 1.44 1.36 1.28 1.21 1.13 4.64 4.55 4.45 4.36 4.27 4.17 4.08 3.99 3.89 3.80 3.71 3.61 3.52 3.43 3.34 3.24 3.15 3.06 2.96 2.86 2.76 2.67 2.57 2.47 2.37 2.27 2.17 2.07 1.97 1.87 1.77 1.67 1.57 1.47 1.37 1.27 5.19 5.09 4.99 4.88 4.78 4.67 4.57 4.46 4.36 4.26 4.15 4.05 3.94 3.84 3.73 3.63 3.53 3.42 3.32 3.21 3.09 2.98 2.87 2.76 2.65 2.54 2.43 2.32 2.21 2.09 1.98 1.87 1.76 1.65 1.54 1.43 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
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Table 43: Pipelined Multiplier Switching Characteristics Speed Grade Description
Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin35 Clock to Pin34 Clock to Pin33 Clock to Pin32 Clock to Pin31 Clock to Pin30 Clock to Pin29 Clock to Pin28 Clock to Pin27 Clock to Pin26 Clock to Pin25 Clock to Pin24 Clock to Pin23 Clock to Pin22 Clock to Pin21 Clock to Pin20 Clock to Pin19 Clock to Pin18 Clock to Pin17 Clock to Pin16 Clock to Pin15 Clock to Pin14 Clock to Pin13 Clock to Pin12 Clock to Pin11 Clock to Pin10 Clock to Pin9 Clock to Pin8 Clock to Pin7 Clock to Pin6 Clock to Pin5 Clock to Pin4 Clock to Pin3 Clock to Pin2 Clock to Pin1 Clock to Pin0 TMULTCK_P35 TMULTCK_P34 TMULTCK_P33 TMULTCK_P32 TMULTCK_P31 TMULTCK_P30 TMULTCK_P29 TMULTCK_P28 TMULTCK_P27 TMULTCK_P26 TMULTCK_P25 TMULTCK_P24 TMULTCK_P23 TMULTCK_P22 TMULTCK_P21 TMULTCK_P20 TMULTCK_P19 TMULTCK_P18 TMULTCK_P17 TMULTCK_P16 TMULTCK_P15 TMULTCK_P14 TMULTCK_P13 TMULTCK_P12 TMULTCK_P11 TMULTCK_P10 TMULTCK_P9 TMULTCK_P8 TMULTCK_P7 TMULTCK_P6 TMULTCK_P5 TMULTCK_P4 TMULTCK_P3 TMULTCK_P2 TMULTCK_P1 TMULTCK_P0 2.45 2.36 2.28 2.20 2.12 2.03 1.95 1.87 1.79 1.70 1.62 1.54 1.46 1.37 1.29 1.21 1.13 1.04 0.96 0.88 0.80 0.71 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 2.92 2.82 2.72 2.62 2.52 2.42 2.32 2.22 2.12 2.02 1.92 1.82 1.71 1.61 1.51 1.41 1.31 1.21 1.11 1.01 0.91 0.81 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 3.27 3.16 3.05 2.93 2.82 2.71 2.60 2.48 2.37 2.26 2.15 2.03 1.92 1.81 1.69 1.58 1.47 1.36 1.24 1.13 1.02 0.91 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 0.79 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max TMULIDCK/TMULCKID TMULIDCK_CE/TMULCKID_CE TMULIDCK_RST/TMULCKID_RST 1.86/ 0.00 0.23/ 0.00 0.21/-0.09 2.06/ 0.00 0.25/ 0.00 0.24/-0.09 2.31/ 0.00 0.28/ 0.00 0.26/-0.10 ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
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Block SelectRAM+ Switching Characteristics
Table 44: Block SelectRAM+ Switching Characteristics Speed Grade Description
Sequential Delays Clock CLK to DOUT output Setup and Hold Times Before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK CLKA to CLKB setup time for different ports Minimum Pulse Width, High Minimum Pulse Width, Low TBCCS TBPWH TBPWL 1.0 1.17 1.17 1.0 1.30 1.30 1.0 1.50 1.50 ns, min ns, min ns, min TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE TBRCK/TBCKR TBWCK/TBCKW 0.27/ 0.22 0.20/ 0.22 0.28/ 0.00 0.28/ 0.00 0.33/ 0.00 0.31/ 0.25 0.23/ 0.25 0.32/ 0.00 0.32/ 0.00 0.35/ 0.00 0.35/ 0.28 0.26/ 0.28 0.35/ 0.00 0.35/ 0.00 0.39/ 0.00 ns, min ns, min ns, min ns, min ns, min TBCKO 1.41 1.50 1.68 ns, max
Symbol
-7
-6
-5
Units
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
TBUF Switching Characteristics
Table 45: TBUF Switching Characteristics Speed Grade Description
Combinatorial Delays IN input to OUT output TRI input to OUT output high-impedance TRI input to valid data on OUT output TIO TOFF TON 0.88 0.48 0.48 1.01 0.55 0.55 1.12 0.61 0.61 ns, max ns, max ns, max
Symbol
-7
-6
-5
Units
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Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in Figure 7; corresponding timing characteristics are listed in Table 46.
VCC
1 TPOR
PROG_B
2 TPL
INIT_B
3
TICCK
CCLK (Output or Input) M0, M1, M2* (Required) *Can be either 0 or 1, but must not toggle during and after configuration.
ds083-3_07_012004
Figure 7: Configuration Power-Up Timing Table 46: Power-Up Timing Characteristics Description Power-on reset Program latency CCLK (output) delay Program pulse width Figure References 1 2 3 Symbol TPOR TPL TICCK TPROGRAM Value TPL + 2 4 0.25 4.00 300 Units ms, max
s per frame, max s, min s, max
ns, min
Notes: 1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to ground or VCCAUX. The mode pins should not be toggled during and after configuration.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Master/Slave Serial Mode Parameters
Clock timing for Slave Serial configuration programming is shown in Figure 8, with Master Serial clock timing shown in Figure 9. Programming parameters for both Slave and Master modes are given in Table 47.
Serial DIN
1 TDCC 2 TCCD 5 TCCL
CCLK
4 TCCH 3 TCCO
Serial DOUT
ds083-3_08_111104
Figure 8: Slave Serial Mode Timing Sequence
CCLK (Output) 2 TCKDS 1 TDSCK Serial DIN
Serial DOUT
ds083-3_09_111104
Figure 9: Master Serial Mode Timing Sequence
.
Table 47: Master/Slave Serial Mode Timing Characteristics Description DIN setup/hold, slave mode (Figure 8) DIN setup/hold, master mode (Figure 9) DOUT High time CCLK Low time Maximum start-up frequency Maximum frequency Frequency tolerance, master mode with respect to nominal Figure References 1/2 1/2 3 4 5 Symbol TDCC/TCCD TDSCK/TCKDS TCCO TCCH TCCL FCC_STARTUP FCC_SERIAL Value 5.0/0.0 5.0/0.0 12.0 5.0 5.0 50 66 (1) +45% -30% Units ns, min ns, min ns, max ns, min ns, min MHz, max MHz, max
Notes: 1. If no provision is made in the design to adjust the frequency of CCLK, FCC_SERIAL should not exceed FCC_STARTUP.
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Master/Slave SelectMAP Parameters
Figure 10 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the Virtex-II Pro Platform FPGA User Guide.
CCLK 3 TSMCSCC 5 TSMCCW 1 TSMDCC DATA[0:7] 7 BUSY TSMCKBY 2 TSMCCD
CS_B
4
TSMCCCS
RDWR_B
6
TSMWCC
No Write
Write
No Write
Write
ds083-3_10_012004
Figure 10: SelectMAP Mode Data Loading Sequence (Generic) Table 48: SelectMAP Mode Write Timing Characteristics Description Device
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20
Figure References
Symbol
Value 5.0/0.0 5.0/0.0 5.0/0.0 5.0/0.0 5.0/0.0
Units ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, max MHz, max MHz, max MHz, max
DATA[0:7] setup/hold
XC2VP30 XC2VP40 XC2VP50
1/2
TSMDCC/TSMCCD
5.0/0.0 5.0/0.0 5.0/0.0 6.0/0.0 6.0/0.0 7.5/0.0
CCLK
XC2VP70 XC2VPX70 XC2VP100
CS_B setup/hold RDWR_B setup/hold BUSY propagation delay Maximum start-up frequency Maximum frequency Maximum frequency with no handshake
3/4 5/6 7
TSMCSCC/TSMCCCS TSMCCW/TSMWCC TSMCKBY FCC_STARTUP FCC_SELECTMAP FCCNH
7.0/0.0 7.0/0.0 12.0 50 50 50
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
JTAG Test Access Port Switching Characteristics
Characterization data for some of the most commonly requested timing parameters shown in Figure 11 is listed in Table 49.
FI
TMS
TDI 1 TTAPTCK TCK 3 TTCKTDO TDO Data Valid 2 TTCKTAP
Data to be captured
Data to be driven out
Data Valid
ds083-3_11_012104
Figure 11: Virtex-II Pro Boundary Scan Port Timing Waveforms Table 49: Boundary-Scan Port Timing Specifications Description TMS and TDI setup time TCK TMS and TDI hold times Falling edge to TDO output valid Maximum frequency Figure References 1 2 3 Symbol TTAPTCK TTCKTAP TTCKTDO FTCK Value 5.5 2.0 11.0 33.0 Units ns, min ns, min ns, max MHz, max
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM
Table 50: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Speed Grade Description
LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 26. Global Clock and OFF with DCM TICKOFDCM XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 1.55 1.58 1.63 1.68 1.68 1.68 1.71 1.80 1.87 1.87 N/A 1.59 1.61 1.68 1.74 1.74 1.75 1.86 2.00 2.07 2.07 2.38 1.62 1.65 1.72 1.79 1.79 1.80 1.92 2.07 2.24 2.24 2.45 ns ns ns ns ns ns ns ns ns ns ns
Symbol
Device
-7
-6
-5
Units
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with test setup shown in Figure 6. For other I/O standards, see Table 37. 3. DCM output jitter is already included in the timing calculation.
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Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM
Table 51: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Speed Grade Description
LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 26. Global Clock and OFF without DCM TICKOF XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 3.19 3.39 3.59 3.62 3.62 3.73 3.89 4.00 4.38 4.38 N/A 3.52 3.91 4.00 4.08 4.08 4.12 4.28 4.43 4.87 4.87 5.32 3.82 4.27 4.36 4.46 4.46 4.50 4.67 4.84 5.33 5.33 5.82 ns ns ns ns ns ns ns ns ns ns ns
Symbol
Device
-7
-6
-5
Units
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with test setup shown in Figure 6. For other I/O standards, see Table 37. 3. DCM output jitter is already included in the timing calculation.
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Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Table 52: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM Speed Grade Description
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 23. No Delay Global Clock and IFF (2) with DCM TPSDCM/TPHDCM XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 1.54/-0.58 1.59/-0.59 1.66/-0.61 1.68/-0.53 1.68/-0.53 1.81/-0.74 1.85/-0.65 1.85/-0.57 1.86/-0.45 1.86/-0.45 N/A 1.54/-0.57 1.59/-0.58 1.66/-0.59 1.68/-0.53 1.68/-0.53 1.81/-0.74 1.85/-0.64 1.85/-0.54 1.86/-0.39 1.86/-0.39 1.86/-0.35 1.54/-0.56 1.59/-0.57 1.66/-0.57 1.68/-0.50 1.68/-0.50 1.81/-0.71 1.85/-0.60 1.85/-0.50 1.86/-0.30 1.86/-0.30 1.87/-0.28 ns ns ns ns ns ns ns ns ns ns ns
Symbol
Device
-7
-6
-5
Units
Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. These measurements include:
CLK0 and CLK180 DCM jitter Worst-case duty-cycle distortion using CLK0 and CLK180, TDCD_CLK180 .
3. IFF = Input Flip-Flop or Latch
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Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
,
Table 53: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM Speed Grade Description
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 23. Full Delay Global Clock and IFF without DCM TPSFD/TPHFD XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 1.80/-0.44 1.82/-0.53 1.80/-0.34 1.76/-0.24 1.76/-0.24 1.75/-0.22 2.25/-0.54 2.93/-1.02 2.79/-0.72 2.79/-0.72 N/A 1.85/-0.41 1.83/-0.31 1.81/-0.24 1.83/-0.17 1.83/-0.17 1.92/-0.26 2.40/-0.56 2.98/-0.93 2.79/-0.55 2.79/-0.55 5.58/-2.35 1.96/-0.43 1.90/-0.29 1.88/-0.19 1.92/-0.15 1.92/-0.15 1.99/-0.23 2.49/-0.54 3.00/-0.83 2.78/-0.41 2.78/-0.41 5.60/-2.35 ns ns ns ns ns ns ns ns ns ns ns
Symbol
Device
-7
-6
-5
Units
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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DCM Timing Parameters
All devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. All output jitter and phase specifications are determined through statistical measurement at the package pins.
Operating Frequency Ranges
e
Table 54: Operating Frequency Ranges Speed Grade Description Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270 CLK2X180 (5,6) CLKOUT_FREQ_1X_LF_MIN CLKOUT_FREQ_1X_LF_MAX CLK2X, CLKOUT_FREQ_2X_LF_MIN CLKOUT_FREQ_2X_LF_MAX CLKDV CLKOUT_FREQ_DV_LF_MIN CLKOUT_FREQ_DV_LF_MAX CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_MIN CLKOUT_FREQ_FX_LF_MAX
Symbol
Constraints
-7
24.00 270.00 48.00 450.00 1.50 140.00 24.00 240.00
-6
24.00 210.00 48.00 420.00 1.50 140.00 24.00 240.00
-5
24.00 180.00 48.00 360.00 1.50 120.00 24.00 210.00
Units
MHz MHz MHz MHz MHz MHz MHz MHz
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs) (1,3,4) outputs) (2,3,4) CLKIN_FREQ_DLL_LF_MIN CLKIN_FREQ_DLL_LF_MAX CLKIN (using CLKFX CLKIN_FREQ_FX_LF_MIN CLKIN_FREQ_FX_LF_MAX PSCLK PSCLK_FREQ_LF_MIN PSCLK_FREQ_LF_MAX
24.00 270.00 1.00 240.00 0.01 450.00
24.00 210.00 1.00 240.00 0.01 420.00
24.00 180.00 1.00 210.00 0.01 360.00
MHz MHz MHz MHz MHz MHz
Output Clocks (High Frequency Mode)
CLK0, CLK180 (6) CLKOUT_FREQ_1X_HF_MIN CLKOUT_FREQ_1X_HF_MAX CLKDV CLKOUT_FREQ_DV_HF_MIN CLKOUT_FREQ_DV_HF_MAX CLKFX, CLKFX180 CLKOUT_FREQ_FX_HF_MIN CLKOUT_FREQ_FX_HF_MAX
48.00 450.00 3.00 280.00 210.00 320.00
48.00 420.00 3.00 280.00 210.00 320.00
48.00 360.00 3.00 240.00 210.00 270.00
MHz MHz MHz MHz MHz MHz
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs) (1,3,4,6) outputs) (2,3,4) CLKIN_FREQ_DLL_HF_MIN CLKIN_FREQ_DLL_HF_MAX CLKIN (using CLKFX CLKIN_FREQ_FX_HF_MIN CLKIN_FREQ_FX_HF_MAX
48.00 450.00 50.00 320.00 0.01 450.00
48.00 420.00 50.00 320.00 0.01 420.00
48.00 360.00 50.00 270.00 0.01 360.00
MHz MHz MHz MHz
PSCLK
PSCLK_FREQ_HF_MIN PSCLK_FREQ_HF_MAX
MHz MHz
Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values. 4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within 5% (45/55 to 55/45). 5. CLK2X and CLK2X180 may not be used as the input to the CLKFB pin. See the Virtex-II Pro Platform FPGA User Guide for more information. 6. For the XC2VP100 -6 device only, clock macros for corner DCMS (X0Y0, X5Y0, X0Y1, X5Y1) are required to operate at maximum clock frequency. See XAPP685 for implementation examples.
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Input Clock Tolerances
Table 55: Input Clock Tolerances Speed Grade Constraints Description
Input Clock Low/High Pulse Width
PSCLK PSCLK_PULSE < 1MHz 1 - 10 MHz 10 - 25 MHz 25 - 50 MHz 50 - 100 MHz 100 - 150 MHz PSCLK and CLKIN(3) PSCLK_PULSE and CLKIN_PULSE 150 - 200 MHz 200 - 250 MHz 250 - 300 MHz 300 - 350 MHz 350 - 400 MHz > 400 MHz 25.00 25.00 10.00 5.00 3.00 2.40 2.00 1.80 1.50 1.30 1.15 1.05 25.00 25.00 10.00 5.00 3.00 2.40 2.00 1.80 1.50 1.30 1.15 1.05 25.00 25.00 10.00 5.00 3.00 2.40 2.00 1.80 1.50 1.30 1.15 1.05 ns ns ns ns ns ns ns ns ns ns ns ns
-7 Min Max Min
-6 Max Min
-5 Max Units
Symbol
FCLKIN
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF 300 300 300 300 300 300 ps ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF 150 150 150 150 150 150 ps ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_FX_LF 1 1 1 1 1 1 ns ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using CLKFX outputs)(2) CLKIN_PER_JITT_DLL_HF CLKIN_PER_JITT_FX_HF 1 1 1 1 1 1 ns ns
Feedback Clock Path Delay Variation
CLKFB off-chip feedback CLKFB_DELAY_VAR_EXT 1 1 1 ns
Notes:
1. 2. 3. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. If both DLL and CLKFX outputs are used, follow the more restrictive specification. If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within 5% (45/55 to 55/45).
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Output Clock Jitter
Table 56: Output Clock Jitter Speed Grade Description
Clock Synthesis Period Jitter
CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 CLKOUT_PER_JITT_FX 100 150 150 150 200 150 300
Note (1)
Symbol
Constraints
-7
-6
-5
Units
100 150 150 150 200 150 300
Note (1)
100 150 150 150 200 150 300
Note (1)
ps ps ps ps ps ps ps ps
Notes: 1. Use the Jitter Calculator on the Xilinx website (http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm) for CLKFX and CLKFX180 output jitter.
Output Clock Phase Alignment
Table 57: Output Clock Phase Alignment Speed Grade Description
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB CLKIN_CLKFB_PHASE 50 50 50 ps
Symbol
Constraints
-7
-6
-5
Units
Phase Offset Between Any DCM Outputs
All CLK* outputs CLKOUT_PHASE 140 140 140 ps
Duty Cycle Precision
DLL outputs(1) CLKFX outputs CLKOUT_DUTY_CYCLE_DLL(2) CLKOUT_DUTY_CYCLE_FX 150 100 150 100 150 100 ps ps
Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. 3. Specification also applies to PSCLK.
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Miscellaneous Timing Parameters
Table 58: Miscellaneous Timing Parameters Speed Grade Description
Time Required to Achieve LOCK
Using DLL outputs (1) LOCK_DLL: LOCK_DLL_60 LOCK_DLL_50_60 LOCK_DLL_40_50 LOCK_DLL_30_40 LOCK_DLL_24_30 Using CLKFX outputs LOCK_FX_MIN LOCK_FX_MAX Additional lock time with fine phase shifting LOCK_DLL_FINE_SHIFT > 60MHz 50 - 60 MHz 40 - 50 MHz 30 - 40 MHz 24 - 30 MHz 20.00 25.00 50.00 90.00 120.00 10.00 10.00 50.00 20.00 25.00 50.00 90.00 120.00 10.00 10.00 50.00 20.00 25.00 50.00 90.00 120.00 10.00 10.00 50.00 us us us us us ms ms us
Symbol
Constraints FCLKIN
-7
-6
-5
Units
Fine Phase Shifting
Absolute shifting range FINE_SHIFT_RANGE 10.00 10.00 10.00 ns
Delay Lines
Tap delay resolution DCM_TAP_MIN DCM_TAP_MAX 30.00 50.00 30.00 50.00 30.00 50.00 ps ps
Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Frequency Synthesis
Table 59: Frequency Synthesis Attribute
CLKFX_MULTIPLY CLKFX_DIVIDE
Min
2 1
Max
32 32
Parameter Cross-Reference
Table 60: Parameter Cross-Reference Libraries Guide
DLL_CLKOUT_{MIN|MAX}_LF DFS_CLKOUT_{MIN|MAX}_LF DLL_CLKIN_{MIN|MAX}_LF DFS_CLKIN_{MIN|MAX}_LF DLL_CLKOUT_{MIN|MAX}_HF DFS_CLKOUT_{MIN|MAX}_HF DLL_CLKIN_{MIN|MAX}_HF DFS_CLKIN_{MIN|MAX}_HF CLKOUT_FREQ_FX_LF CLKIN_FREQ_DLL_LF CLKIN_FREQ_FX_LF CLKOUT_FREQ_{1X|DV}_HF CLKOUT_FREQ_FX_HF CLKIN_FREQ_DLL_HF CLKIN_FREQ_FX_HF
Data Sheet
CLKOUT_FREQ_{1X|2X|DV}_LF
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Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro source-synchronous transmitter and receiver data-valid windows. Table 61: Duty Cycle Distortion and Clock-Tree Skew Speed Grade Description
Duty Cycle Distortion (1)
Symbol
TDCD_LOCAL TDCD_CLK180
Device
All
-7 0.10 0.10
-6 0.10 0.11 0.13 0.13 0.13 0.21 0.21 0.22 0.34 0.41 0.59 0.59 0.79
-5 0.20 0.13 0.13 0.13 0.13 0.22 0.22 0.24 0.35 0.42 0.64 0.64 0.87
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns
Clock Tree
Skew (2)
TCKSKEW
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
0.13 0.13 0.13 0.20 0.20 0.20 0.33 0.40 0.54 0.54 N/A
Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. TDCD_LOCAL applies to cases where the dedicated path from the DCM to the BUFG is bypassed and where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O. Users must follow the implementation guidelines contained in XAPP685 for these specifications to apply. TDCD_CLK180 applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element in the I/O. 2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
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Table 62: Package Skew Description
Package Skew(1)
Symbol
TPKGSKEW
Device/Package
XC2VP2FF672 XC2VP4FF672 XC2VP7FF672 XC2VP7FF896 XC2VP20FF896 XC2VPX20FF896 XC2VP20FF1152 XC2VP30FF896 XC2VP30FF1152 XC2VP40FF1152 XC2VP40FF1148 XC2VP50FF1152 XC2VP50FF1148 XC2VP50FF1517 XC2VP70FF1517 XC2VP70FF1704 XC2VPX70FF1704 XC2VP100FF1704 XC2VP100FF1696
Value
104 102 92 101 93 93 106 86 112 92 100 88 101 97 95 101 101 86 100
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes: 1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball (7.1ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 63: Sample Window Speed Grade Description
Sampling Error at Receiver Pins(1)
Symbol
TSAMP
Device
All
-7 0.50
-6 0.50
-5 0.50
Units
ns
Notes: 1. This parameter indicates the total sampling error of Virtex-II Pro DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. 2. These measurements include: - CLK0 and CLK180 DCM jitter - Worst-case duty-cycle distortion, TDCD_CLK180 - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew.
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Table 64: Example Pin-to-Pin Setup/Hold: Source-Synchronous Configuration Speed Grade Description
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM and Global Clock Buffer. Values represent an 18-bit bus located in Banks 2, 3, 6, or 7 and grouped to one Horizontal Global Clock Line. TRACE must be used to determine the actual values for any given design. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Input Switching Characteristics Standard Adjustments, page 23. No Delay Global Clock and IFF (2) with DCM TPSDCM_0/TPHDCM_0 XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 0.23/0.39 0.26/0.37 0.18/ 0.36 0.14/ 0.41 0.14/ 0.41 0.29/ 0.25 0.25/ 0.30 0.18/ 0.36 0.18/ 0.37 0.18/ 0.37 N/A 0.21/0.42 0.24/0.40 0.18/ 0.40 0.13/ 0.42 0.13/ 0.42 0.31/ 0.24 0.26/ 0.29 0.18/ 0.38 0.18/ 0.38 0.18/ 0.38 0.18/ 0.33 0.21/0.42 0.24/0.41 0.18/ 0.41 0.12/ 0.44 0.12/ 0.44 0.31/ 0.24 0.27/ 0.29 0.17/ 0.39 0.18/ 0.38 0.18/ 0.38 0.19/ 0.37 ns ns ns ns ns ns ns ns ns ns ns
Symbol
Device
-7
-6
-5
Units
Notes: 1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include:
CLK0 and CLK180 DCM jitter Worst-case duty-cycle distortion using CLK0 and CLK180, TDCD_CLK180
Package skew is not included in these measurements. 2. IFF = Input Flip-Flop
Source Synchronous Timing Budgets
This section describes how to use the parameters provided in the Source-Synchronous Switching Characteristics section to develop system-specific timing budgets. The following analysis provides information necessary for determining Virtex-II Pro contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol Interference or PCB skew.
Notes: 1. Jitter values and accumulation methodology to be provided in a future release of this document. The absolute period jitter values found in the DCM Timing Parameters section of the particular DCM output clock used to clock the IOB FF can be used for a best case analysis. 2. This value depends on the clocking methodology used. See Note1 for Table 61. 3. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. 4. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball.
Virtex-II Pro Transmitter Data-Valid Window (TX)
TX is the minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: TX = Data Period - [Jitter(1) + Duty Cycle Distortion(2) + TCKSKEW(3) + TPKGSKEW(4)]
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Worst-case duty-cycle distortion DCM accuracy (phase offset) DCM phase shift resolution. These measurements do not include package or clock tree skew. 2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. 3. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball.
Virtex-II Pro Receiver Data-Valid Window (RX)
RX is the required minimum aggregate valid data period for a source-synchronous data bus at the pins of the device and is calculated as follows: RX = [TSAMP(1) + TCKSKEW(2) + TPKGSKEW(3) ]
Notes: 1. This parameter indicates the total sampling error of Virtex-II Pro DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 and CLK180 DCM jitter in a quiet system
Revision History
This section records the change history for this module of the data sheet. Date 01/31/02 06/17/02 Version 1.0 2.0 Initial Xilinx release. * * * * * * * * * 09/27/02 11/20/02 2.2 2.3 Added new Virtex-II Pro family members. Added timing parameters from speedsfile v1.62. Added Table 43, Pipelined Multiplier Switching Characteristics. Added 3.3V-vs-2.5V table entries for some parameters. Added Source-Synchronous Switching Characteristics section. Added absolute max ratings for 3.3V-vs-2.5V parameters in Table 1. Added recommended operating conditions for VIN and RocketIO footnote to Table 2. Updated SSTL2 values in Table 6. Added SSTL18 values: Table 6, Table 36, Table 32. [Table 32 removed in v2.8.] Added Table 10, which contains LVPECL DC specifications. Revision
09/03/02
2.1
Added section General Power Supply Requirements. Updated parametric information in: * Table 1: Increase Absolute Max Rating for VCCO , VREF, VIN, and VTS from 3.6V to 3.75V. Delete cautionary footnotes related to voltage overshoot/undershoot. * Table 2: Delete VCCO specifications for 2.5V and below operation. Delete footnote referencing special information for 3.3V operation. Add footnote for PCI/PCI-X. * Table 3: Add IBATT. Delete IL specifications for 2.5V and below operation. * Table 4: Add Typical Quiescent Supply Currents for XC2VP4 and XC2VP7 only * Table 6: Correct IOL and IOH for SSTL2 I. Add rows for LVTTL, LVCMOS33, and PCI-X. Correct max VIH from VCCO to 3.6V. * Table 7: Correct Min/Max VOD, VOCM, and VICM * Table 10: Reformat LVPECL DC Specifications to match Virtex-II data sheet format * Table 12: Correct parameter name from Differential Output Voltage to Single-Ended Output Voltage Swing. * Table 16: Add CPMC405CLOCK max frequencies * Table 27: Add footnote regarding serial data rate limitation in -5 part. * Table 36: Add rows for LVTTL, LVCMOS33, and PCI-X. * Table 32: Add LVTTL, LVCMOS33, and PCI-X. Correct all capacitive load values (except PCI/PCI-X) to 0 pF. [Table 32 removed in v2.8.] * Table 48: Correct CCLK max frequencies Table 1: Correct lower limit of voltage range of VIN and VTS from -0.3V to -0.5V for 3.3V.
11/25/02
2.4
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Date 12/03/02
Version 2.5
Revision Updated parametric information in: * Table 1: Correct lower limit of voltage range of VIN and VTS from -0.5V to -0.3V for 3.3V. * Table 2: Add footnote (2) regarding VCCAUX voltage droop. Renumbered other notes. * Table 12: Add waveform diagrams (Figure 1 and Figure 2) illustrating DVOUT (single-ended) and DVPPOUT (differential). * Table 23: Indicate REFCLK upper frequency limitation; relate REFCLK parameters to REFCLK2, BREFCLK, and BREFCLK2; correct TRCLK and TFCLK values and unit of measurement. * Table 57: Add qualifying footnote to CLKOUT_DUTY_CYCLE_DLL. Updated parametric information in: * Table 12: Correct DVIN Min (200 mV to 175 mV) and DVIN Max (1000 mV to 2000 mV). * Table 23: Correct TRCLK /TFCLK Typ (400 ps to 600 ps) and Max (600 ps to 1000 ps). Add footnote (2) to qualify Max TGJTT parameter. * Table 56: Correct hyperlink in footnote (1) to point directly to Answer Record 13645. * Move clock parameters from Table 18, Table 19, Table 20, and Table 21 to Table 16. * * * * * * * * * * * * * * * * Added/updated timing parameters from speedsfile v1.76. Table 2: Delete first table footnote and renumber all others. Table 3: Add "sample-tested" to IL. Remove "Device" column, unnecessary. Table 8: Update VOCM (Typ) to 1.250V. Table 10: Update LVPECL_25 DC parameters. Table 23: Update FGCLK frequency ranges. Break out TGJTT by operating speed. Table 27: Update FGTX frequency ranges. Correct TDJ to 0.17 UI, TRJ to o.18 UI. Table 36: Update VREF (Typ) for HSTL Class I/II from 1.08V to 0.90V. Table 40, Table 41: Correct parameter name "CE input (WS)" to "SR input". Table 61: Break out TDCD_CLK0 by device type. Updated time and frequency parameters as per speedsfile v1.78. Table 3: Added values for IREF, IL, IRPU, IRPD Corrected ICCINTQ (Table 4) and ICCINTMIN (Table 5) for XC2VP20 to 600 mA. Table 4: Updated/Added Typ and Max quiescent current values for XC2VP7 and XC2VP20. Added footnote specifying parameters are for Commercial Grade parts. Table 5: Added footnote specifying parameters are for Commercial Grade parts. Table 6: Corrected VIH (Max) for LVTTL and LVCMOS33 standards from 3.6V to 3.45V. Changed VIL (Min) for all standards to -0.2V. Corrected VIL (Max) for LVCMOS15 and LVCMOS18 from 20% VCCO to 30% VCCO . Table 10: Corrected LVPECL_25 Min and Max values for VIH and VIL. Added explanatory text above table. Table 13 and Table 14 (pin-pin and reg-reg performance): Changed device specified from XC2VP7FF672-6 to XC2VP20FF1152-6. Table 15: Updated to show devices XC2VP7 and XC2VP20 as Preliminary for the -6 speed grade and Production for the -5 speed grade. Removed former Table 32, Standard Capacitive Loads. Table 49: Updated TTAPTCK from 4.0 ns to 5.5 ns. Table 56: Modified footnote referenced at CLKFX/CLKFX180 to point to the online Jitter Calculator. Added Figure 6 and accompanying procedure for measuring standard adjustments. Table 1: Footnote (2) rewritten to specify "one or more banks." Table 54: Some DCM parameters were erroneously missing from v2.8 (single-module version) due to a document compilation error. The concatenated full data sheet version was not affected. These parameters have been restored.
01/20/03
2.6
03/24/03
2.7
05/27/03
2.8
* * * * * * * 05/27/03 (cont'd) 2.8 (cont'd) * *
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Date 08/25/03
Version 2.9 * * * * *
Revision Updated time and frequency parameters as per speedsfile v1.81. Table 1: Footnote (2) rewritten to specify "one or more banks." Table 2: Added footnote referring to XAPP659 for 3.3V I/O operation. Table 50 and Table 51: Revised test setup footnote to refer to Figure 6. Previously specified a capacitive load parameter. Table 54: Due to a document compilation error in v2.8, some DCM parameters were erroneously omitted from the full data sheet file (all four modules concatenated), though not from the stand-alone Module 3 file. The omitted parameters have been restored. Table 61 and Table 63: Corrected parameters to expression in picoseconds, as labeled. Previously expressed in nanoseconds, but labeled picoseconds. Figure 6: Added note to figure regarding termination resistors. Table 5: Added ICCINTMIN for XC2VP30 device. Figure 7: Changed representation of mode pins M0, M1, and M2 indicating that they must be held to a constant DC level during and after configuration. Table 46: Added footnote indicating that mode pins M0, M1, and M2 must be held to a constant DC level during and after configuration. Table 1: Deleted Footnote (2), which had derated the absolute maximum TJ when one or more banks operated at 3.3V. Changed TJ description from "Operating junction temperature" to "Maximum junction temperature". Added new Footnote (2) linking to website for package thermal data. Table 4 and Table 5: Filled in power-on and quiescent current parameters for all devices through XC2VP70. Added Industrial Grade multiplier specification to Footnote (1) in both tables. In section General Power Supply Requirements, replaced reference to Answer Record 11713 with reference to XAPP689 regarding handling of simultaneously switching outputs (SSO). In section I/O Standard Adjustment Measurement Methodology: - Table 36 renamed Input Delay Measurement Methodology. Added footnotes. - Added new Table 37, Output Delay Measurement Methodology. - Replaced Figure 6, Generalized Test Setup, with new drawing. - Revised and extended text describing output delay measurement procedure. Table 55: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing Footnote (2) to new Footnote (3). Table 1: Changed 3.3V absolute max VIN and VTS from 3.75V to 4.05V. Added footnote referring to XAPP659. Table 4: Removed MIN column from table. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, updated and released to Production status as per speedsfile v1.83. Featured changes: - Speedsfile parameter values for -7 speed grade added for devices XC2VP2-XC2VP70. - Table 13 and Table 14: Pin-to-pin and register-to_register performance parameter values added. - Table 61: New parameter TDCD_LOCAL (and footnote) replaces TDCD_CLK0. - All remaining source-synchronous parameter values added (Table 61 & following).
* * * 09/10/03 2.10 * * 10/14/03 2.11 *
*
*
*
* 11/10/03 2.12 * * 12/05/03 3.0 *
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Date 12/05/03 (cont'd)
Version 3.0 (cont'd) * * * * * * * * * * * * * * *
Revision Non-speedsfile parameter values added or updated: Table 3: IBATT . Table 4: For XC2VP100, ICCINTQ, ICCOQ, and ICCAUXQ . Table 5: For XC2VP100, ICCINTMIN . Table 17: TCPWL and TCPWH . Table 25: Added explanatory footnote to TRXLAT (MGT receiver latency) max value. Table 54: Added Footnote (3) regarding use of CLKIN_DIVIDE_BY_2 attribute. Updated time and frequency parameters as per speedsfile v1.85. Table 2, Recommended Operating Conditions: Revised Footnotes (4) and (6). Table 4, Quiescent Supply Current: Added Footnote (1) and updated Typical parameters. Table 10, LVPECL DC Specifications: Added parameter values for Maximum Differential Input Voltage (LVPECL). Table 14, Register-to-Register Performance: Removed reference to a number of designs for which test data is no longer provided. Table 16, Processor Clocks Absolute AC Characteristics: Added Footnote (1) referring to XAPP755. Added Table 38, Clock Distribution Switching Characteristics. Revised section Configuration Timing, page 37 through page 39, and JTAG Test Access Port Switching Characteristics, page 40, with improved timing diagrams, parameter tables, and organization. Table 47, Master/Slave Serial Mode Timing Characteristics, and Table 48, SelectMAP Mode Write Timing Characteristics: Added parameter FCC_STARTUP. Table 48, SelectMAP Mode Write Timing Characteristics: Broke out TSMDCC/TSMCCD , DATA[0:7] setup/hold time, by device, and added new parameter specifications for XC2VP70 and XC2VP100 devices. Table 54, Operating Frequency Ranges: Added callouts for existing Footnote (3) to the four CLKIN parameters. Added new Footnote (4) to the four CLKIN parameters. Added new Footnote (5) to CLK2X, CLK2X180. Added new Footnote (6) to CLK2X, CLK2X180; CLK0, CLK180; and CLKIN (using DLL outputs). Recompiled for backward compatibility with Acrobat 4 and above. No content changes. Table 2, Recommended Operating Conditions: Corrected VTTX/VTRX lower voltage limit from 1.8V to 1.6V. Table 5, Power-On Current for Virtex-II Pro Devices: Added Footnote (2) stating that listed ICCOMIN values apply to the entire device (all banks). Table 37, Output Delay Measurement Methodology: Corrected VMEAS for LVTTL from 1.4V to 1.65V. Table 54, Operating Frequency Ranges: Corrected CLKOUT_FREQ_1X_LF_MAX and CLKIN_FREQ_DLL_LF_MAX for -7 devices from 210 MHz to 270 MHz. Table 62, Package Skew: Removed XC2VP40FF1517.
02/19/04
3.1
* *
*
03/09/04 04/22/04
3.1.1 3.2
* * * * * *
06/30/04
4.0
Merged in DS110-3 (Module 3 of Virtex-II Pro X data sheet). This merge added numerous previously unpublished RocketIO X MGT parameters. Specifications in this revision are from speedsfile v1.86.
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Date 11/17/04
Version 4.1 * *
Revision Figure 8, Figure 9: Corrected TCCO / DOUT to refer to the falling edge of CCLK. Table 23: Added Footnote (4) to TPHASE indicating an 8B/10B-type bitstream. Corrected TLOCK from Typ to Max specification. Additional description of "2X oversampling" added to half-rate operation condition for FGCLK, and added Footnote (2) requiring use of oversampling techniques in XAPP572 for serial bit rates under 1 Gb/s. Table 25: Converted bit rate conditions for jitter parameters into four ranges. Added Footnote (2) requiring use of oversampling techniques in XAPP572 for serial bit rates under 1 Gb/s. Table 27: Additional description of "2X oversampling" added to half-speed clock description for FGGTX. Converted bit rate conditions for jitter parameters into four ranges. Added Footnotes (3) and (4) requiring use of oversampling techniques in XAPP572 for serial bit rates under 1 Gb/s. Table 37: Changed capacitance CREF for all PCI/PCI-X standards from 0 pF to 10 pF. Table 46: Added Min/Max specifications for TICCK. Section Power-On Power Supply Requirements, page 5: Added word "monotonically" to description of VCCINT ramp-on requirements. Removed requirement that VCCAUX must be powered on before or with VCCO . Updated values in Virtex-II Pro Performance Characteristics and Virtex-II Pro Switching Characteristics tables, based on values extracted from speedsfile version 1.90. Table 1 and Table 2: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and AVCCAUXRX respectively. Table 3: Further clarified PRXTX (MGT power dissipation) by explaining measurement method in Footnote (3). Table 5: Added power-on current specifications for XC2VPX70 device. Table 22: Changed FGTOL from 100 ppm to 350 ppm. Table 22 and Table 23: Changed TGJTT bit rate qualifiers from fixed bit rates to bit rate ranges. Table 33, Table 35, Table 36, and Table 37: Restructured these I/O-related tables to include descriptions, as well as the actual IOSTANDARD attributes (used in the Xilinx ICETM software) for all I/O standards. Table 33: Rearranged I/O standards in a more logical order. Table 34: Added parameter TRPW (Minimum Pulse Width, SR Input). Table 35: Changed "Csl" to "CREF" to agree with Figure 6 and Table 37. Rearranged I/O standards in a more logical order. Table 36: Added footnote defining equivalents for DCI standards. Table 37: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (CREF) values. Table 44: Added parameter TBCCS, CLKA to CLKB Setup Time. Table 47: Added Footnote (1) indicating that FCC_SERIAL should not exceed FCC_STARTUP if CCLK frequency is not adjustable. Table 49: TTCKTDO corrected from a "Min" to a "Max" specification. Table 12: Added specifications for Differential Input Impedance.
*
*
* * *
03/01/05
4.2
*
* * * * * *
* * * * * * * * 06/20/05 4.3 *
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Date 09/15/05
Version 4.4 * *
Revision Table 2: Added Footnote (7) to AVCCAUXRX for RocketIO X (1.8V for all non-8B/10B-encoded data). Table 3: - Power dissipation for 10.3125 Gb/s deleted. - Max ICCAUXTX and ICCAUXRX specifications added for Virtex-II Pro. Table 11: Added specification for minimum p-p differential input voltage. Table 22: - FGCLK: Changed high end of range to 425 MHz. - TGJTT: Changed measurement units to picoseconds and added maximum specifications for two bit rate ranges. - TLOCK: Changed measurement units to microseconds and adderd typical specification. - TPHASE: Changed measurement units to microseconds and adderd typical and maximum specifications. Table 24: - All parameters: Deleted specifications for 10.3125 Gb/s. - TRJTOL: Added typical specifications. - TJTOL, TSJTOL, and TDDJTOL: Added typical and maximum specifications. Table 26: Restructured table. Total Jitter parameter added. All jitter parameters respecified. Table 28: Restructured table and added new specifications. Changed XC2VPX70 variable baud rate specification to fixed-rate operation at 4.25 Gb/s. Table 15: Removed -7 designations for XC2VPX20 and XC2VPX70 devices.
* *
*
* * 10/10/05 4.5 * * 03/05/07 11/05/07 4.6 4.7
No changes in Module 3 for this revision. Updated copyright notice and legal disclaimer.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules: * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview (Module 1) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description (Module 2) * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics (Module 3) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information (Module 4)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Product Specification * * * * * FF1152 Flip-Chip Fine-Pitch BGA Package FF1148 Flip-Chip Fine-Pitch BGA Package FF1517 Flip-Chip Fine-Pitch BGA Package FF1704 Flip-Chip Fine-Pitch BGA Package FF1696 Flip-Chip Fine-Pitch BGA Package
DS083 (v4.7) November 5, 2007 This document provides VirtexTM-II Pro Device/Package Combinations, Maximum I/Os, and Virtex-II Pro Pin Definitions, followed by pinout tables, for these packages: * * * * * FG256/FGG256 Fine-Pitch BGA Package FG456/FGG456 Fine-Pitch BGA Package FG676/FGG676 Fine-Pitch BGA Package FF672 Flip-Chip Fine-Pitch BGA Package FF896 Flip-Chip Fine-Pitch BGA Package
For device pinout diagrams and layout guidelines, refer to the Virtex-II Pro Platform FPGA User Guide. ASCII package pinout files are also available for download from the Xilinx website (www.xilinx.com).
Virtex-II Pro Device/Package Combinations and Maximum I/Os(1)
Wire-bond and flip-chip packages are available. Table 1 and Table 2 show the maximum number of user I/Os possible in wire-bond and flip-chip packages, respectively. * * * FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). FGG denotes Pb-free wire-bond fine-pitch BGA (1.00 mm pitch). FF denotes flip-chip fine-pitch BGA (1.00 mm pitch)
.
Table 1: Wire-Bond Packages Information Package (1) Pitch (mm) Size (mm) Maximum I/Os FG256/ FGG256 1.00 17 x 17 140 FG456/ FGG456 1.00 23 x 23 248 FG676/ FGG676 1.00 26 x 26 412
Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Pro Ordering Examples (Module 1).
Table 2: Flip-Chip Packages Information Package Pitch (mm) Size (mm) Maximum I/Os FF672 1.00 27 x 27 396 FF896 1.00 31 x 31 556 FF1152 1.00 35 x 35 644 FF1148 1.00 35 x 35 812 FF1517 1.00 40 x 40 964 FF1704 1.00 42.5 x 42.5 1040 FF1696 1.00 42.5 x 42.5 1200
Table 3 shows the number of available I/Os, the number of RocketIOTM (or RocketIO X) multi-gigabit transceiver (MGT) pins, and the number of differential I/O pairs for each Virtex-II Pro device/package combination. The number of I/Os per package includes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, and RSVD), the nine (per transceiver) RocketIO MGT pins (TXP, TXN, RXP, RXN, AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA), and for Virtex-II Pro X devices only, the two BREFCLKN/ BREFCLKP differential clock input pairs (four pins). The Virtex-II Pro X devices are highlighted in bold type.
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
(c) 2002-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 3: Virtex-II Pro Available I/Os and RocketIO MGT Pins per Device/Package Combination Virtex-II Pro Device User I/Os & RocketIO MGT Pins
Available User I/Os
Virtex-II Pro Package (1)
FG256/ FGG256 FG456/ FGG456 FG676/ FGG456
FF672
FF896
FF1152
FF1148
FF1517
FF1704
FF1696
140 36 68 140 36 68 -
156 36 76 248 36 122 248 72 122 -
404 72 196 416 72 202 416 72 202
204 36 100 348 36 172 396 72 196 -
396 72 196 556 72 272 552 72 270 556 72 272 -
564 72 276 644 72 316 692 108 340 692 144 340
804 0 396 812 0 400
852 144 420
-
-
XC2VP2
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VP4
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VP7
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VP20
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VPX20
RocketIO X MGT Pins Differential I/O Pairs Available User I/Os
XC2VP30
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VP40
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VP50
RocketIO MGT Pins Differential I/O Pairs
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 3: Virtex-II Pro Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued) Virtex-II Pro Device User I/Os & RocketIO MGT Pins
Available User I/Os
Virtex-II Pro Package (1)
FG256/ FGG256 FG456/ FGG456 FG676/ FGG456
FF672
FF896
FF1152
FF1148
FF1517
FF1704
FF1696
-
-
-
-
-
-
964 144 476 -
996 180 492 992 180 490 1040 180 512
1164 0 572
XC2VP70
RocketIO MGT Pins Differential I/O Pairs Available User I/Os
XC2VPX70
RocketIO X MGT Pins Differential I/O Pairs Available User I/Os
XC2VP100
RocketIO MGT Pins Differential I/O Pairs
Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Pro Ordering Examples (Module 1)
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Virtex-II Pro Pin Definitions
This section describes the pinouts for Virtex-II Pro devices in the following packages: * * FG256/FGG256, FG456/FGG456, and FG676/FGG676: wire-bond fine-pitch BGA of 1.00 mm pitch FF672, FF896, FF1148, FF1152, FF1517, FF1696, and FF1704: flip-chip fine-pitch BGA of 1.00 mm pitch table per package). Pins that are not available for smaller devices are listed in right-hand columns. Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards. Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table 4 provides definitions for all pin types. All Virtex-II Pro pinout tables are available on the distribution CD-ROM, or on the web (at http://www.xilinx.com).
All of the devices supported in a particular package are pinout-compatible and are listed in the same table (one
Pin Definitions
Table 4 provides a description of each pin type listed in Virtex-II Pro pinout tables. Table 4: Virtex-II Pro Pin Definitions Pin Name User I/O Pins:
IO_LXXY_# Input/Output/ Bidirectional All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled "IO_LXXY_#", where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7)
Direction
Description
Dual-Function Pins:
IO_LXXY_#/ZZZ The dual-function pins are labelled "IO_LXXY_#/ ZZZ", where "ZZZ" can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN - D7, RDWR_B, or CS_B These dual functions are defined in the following section:
"ZZZ" (Dual Function) Definitions:
D0/DIN, D1, D2, D3, D4, D5, D6, D7 CS_B RDWR_B BUSY/DOUT Input/Output * * Input Input Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after configuration.
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. * In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration.
*
INIT_B
Bidirectional (open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. The pin becomes a user I/O after configuration.
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Table 4: Virtex-II Pro Pin Definitions (Continued) Pin Name
GCLKx (S/P)
Direction
Input/Output
Description
These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. These pins can be used to clock the RocketIO transceiver. See the RocketIO Transceiver User Guide for design guidelines and BREFCLK-specific pins, by device.
VRP VRN VREF
Input Input Input
This pin is for the DCI voltage reference resistor of P transistor (per bank). This pin is for the DCI voltage reference resistor of N transistor (per bank). These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank).
Dedicated Pins: (1)
CCLK PROG_B DONE Input/Output Input Input/Output Configuration clock. Output in Master mode or Input in Slave mode. Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. Configuration mode selection. Pin is biased by VCCAUX (must be 2.5V). These pins should not connect to 3.3V unless 100 series resistors are used. The mode pins are not to be toggled (changed) while in operation during and after configuration. Enable I/O pull-ups during configuration. Boundary Scan Clock. This pin is 3.3V compatible. Boundary Scan Data Input. This pin is 3.3V compatible. Boundary Scan Data Output. Pin is open-drain and can be pulled up to 3.3V. It is recommended that the external pull-up be greater than 200. There is no internal pull-up. Boundary Scan Mode Select. This pin is 3.3V compatible.
M2, M1, M0
Input
HSWAP_EN TCK TDI TDO
Input Input Input Output (open-drain) Input
TMS PWRDWN_B
Input Active Low power-down pin (unsupported). Driving this pin Low can adversely affect (unsupported) device operation and configuration. PWRDWN_B is internally pulled High, which is its default state. It does not require an external pull-up.
Other Pins:
DXN, DXP VBATT RSVD VCCO VCCAUX VCCINT GND AVCCAUXRX# AVCCAUXTX# N/A Input N/A Input Input Input Input Input Input Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). Decryptor key memory backup supply. (Connect to VCCAUX or GND if battery not used.) Reserved pin - do not connect. Power-supply pins for the output drivers (per bank). Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Ground. Analog power supply for receive circuitry of the RocketIO MGT (2.5V). Analog power supply for transmit circuitry of the RocketIO MGT (2.5V).
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Table 4: Virtex-II Pro Pin Definitions (Continued) Pin Name
BREFCLKN, BREFCLKP (2) VTRXPAD# VTTXPAD# GNDA# RXPPAD# RXNPAD# TXPPAD# TXNPAD#
Direction
Input Input Input Input Input Input Output Output
Description
Differential clock input that clocks the RocketIO X MGTs populating the same side of the chip (top or bottom). Can also drive DCMs for RocketIO X MGT use. Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V). Transmit termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V). Ground for the analog circuitry of the RocketIO multi-gigabit transceiver. Positive differential receive port of the RocketIO multi-gigabit transceiver. Negative differential receive port of the RocketIO multi-gigabit transceiver. Positive differential transmit port of the RocketIO multi-gigabit transceiver. Negative differential transmit port of the RocketIO multi-gigabit transceiver.
Notes: 1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage). 2. Virtex-II Pro X devices XC2VPX20 and XC2VPX70 only. Each BREFCLK(N/P) differential clock input pair takes the place of one regular Virtex-II Pro dual-function IO/GCLKx(S/P) pair on each side of the chip (top or bottom). For RocketIO BREFCLK, see section BREFCLK Pin Definitions (RocketIO Only) immediately following.
BREFCLK Pin Definitions (RocketIO Only)
These dedicated clocks use the same clock inputs for all packages: BREFCLK Top BREFCLK2 P N P N GCLK4S GCLK5P GCLK2S GCLK3P Bottom BREFCLK2 BREFCLK P N P N GCLK6P GCLK7S GCLK0P GCLK1S
For detailed information about using BREFCLK/BREFCLK2, including routing considerations and pin numbers for all package types, refer to Chapter 2, "Digital Design Considerations," in the RocketIO Transceiver User Guide.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FG256/FGG256 Fine-Pitch BGA Package
As shown in Table 5, XC2VP2 and XC2VP4 Virtex-II Pro devices are available in the FG256/FGG256 fine-pitch BGA package. The pins in each of these devices are identical. Following this table are the FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L06N_0 IO_L06P_0 IO_L07P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number C2 C3 B3 C4 A2 A3 D5 C5 D6 E6 E7 D7 C7 D8 C8 B8 A8
1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L69N_1/VREF_1 IO_L69P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L07N_1 IO_L06N_1 IO_L06P_1 IO_L03N_1/VREF_1 IO_L03P_1
A9 B9 C9 D9 C10 D10 E10 E11 D11 C12 D12 A14 A15
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 1 1 1 1 Pin Description IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 Pin Number C13 B14 C14 C15
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L90N_2 IO_L90P_2
E14 E15 E13 F12 F13 F14 F15 F16 G13 G14 G15 G16 G12 H13 H14 H15 H16 J16
3 3 3 3 3 3 3 3 3 3 3
DS083 (v4.7) November 5, 2007 Product Specification
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L85N_3 IO_L85P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3
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J15 J14 J13 K12 K16 K15 K14 K13 L16 L15 L14
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 3 3 3 3 3 3 3 Pin Description IO_L05P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 Pin Number L13 L12 M13 M16 N16 M15 M14
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07P_4/VREF_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P
P15 P14 R14 P13 T15 T14 N12 P12 N11 M11 M10 N10 P10 N9 P9 R9 T9
5 5 5 5 5 5 5 5 5
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IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L69N_5/VREF_5 IO_L69P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L07N_5/VREF_5
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T8 R8 P8 N8 P7 N7 M7 M6 N6
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 5 5 5 5 5 5 5 5 Pin Description IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number P5 N5 T3 T2 P4 R3 P3 P2
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L85P_6 IO_L85N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6
M3 M2 N1 M1 M4 L5 L4 L3 L2 L1 K4 K3 K2 K1 K5 J4 J3 J2
7 7 7 7 7 7 7
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IO_L90P_7 IO_L90N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L86P_7 IO_L86N_7 IO_L85P_7
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J1 H1 H2 H3 H4 G5 G1
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L85N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 Pin Number G2 G3 G4 F1 F2 F3 F4 F5 E4 E2 E3
0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7
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VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7
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F8 F7 E8 F9 F10 E9 H12 H11 G11 K11 J12 J11 M9 L9 L10 M8 L8 L7 K6 J6 J5 H6 H5
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank 7 Pin Description VCCO_7 Pin Number G6
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7
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N15 D1 P16 N3 N2 P1 D16 E1 E16 C16 N14 C1 D14 D15 D2 D3 B5 B4 A4 A5 C6 A6 A7 B6 B7 B11 B10 A10 A11 C11 A12 A13 B12
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description AVCCAUXRX7 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 Pin Number B13 R13 R12 T13 T12 P11 T11 T10 R10 R11 R7 R6 T7 T6 P6 T5 T4 R4 R5
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND
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N4 N13 M5 M12 E5 E12 D4 D13 R16 R1 B16 B1 T16 T1 R2
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Table 5: FG256/FGG256 -- XC2VP2 and XC2VP4 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number R15 L6 L11 K9 K8 K7 K10 J9 J8 J7 J10 H9 H8 H7 H10 G9 G8 G7 G10 F6 F11 B2 B15 A16 A1
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 1: FG256/FGG256 Fine-Pitch BGA Package Specifications
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FG456/FGG456 Fine-Pitch BGA Package
As shown in Table 6, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FG456/FGG456 fine-pitch BGA package. The pins in these devices are same, except for the differences shown in the "No Connects" column. Following this table are the FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number D5 D6 E6 E7 D7 C7 E8 D8 C8 F9 E9 D9 D10 F10 E10 C10 B11 F11 E11 D11 C11 XC2VP2 XC2VP4 XC2VP7
1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L69N_1/VREF_1 IO_L69P_1 IO_L67N_1 IO_L67P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L07N_1
C12 D12 E12 F12 B12 C13 E13 F13 D13 D14 E14
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 Pin Number F14 C15 D15 E15 C16 D16 E16 E17 D17 D18 XC2VP2 XC2VP4 XC2VP7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L43N_2 IO_L43P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2
C21 C22 D21 D22 E19 E20 E21 E22 F19 F20 F21 F22 F18 G18 G19 G20 G21 G22 H19 H20 H21 H22 H18 J17 J19 J20
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NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L56N_2 IO_L56P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L90N_2 IO_L90P_2 Pin Number J21 J22 J18 K18 K19 K20 K21 K22 K17 L17 L18 L19 L20 L21 XC2VP2 NC NC NC NC NC NC XC2VP4 XC2VP7
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L51N_3/VREF_3 IO_L51P_3
M21 M20 M19 M18 M17 N17 N22 N21 N20 N19 N18 P18 P22 P21 P20 P19 P17 R18 R22 R21 R20 R19
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NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L43N_3 IO_L43P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L69N_4 Pin Number T22 T21 T20 T19 T18 U18 U22 U21 U20 U19 V22 V21 V20 V19 W22 W21 Y22 Y21 AA22 AB21 XC2VP2 NC NC NC NC NC NC NC NC NC NC XC2VP4 XC2VP7
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
W18 W17 V17 V16 W16 Y16 V15 W15 Y15 U14 V14 W14 W13 U13 V13 Y13
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 4 4 4 4 4 Pin Description IO_L69P_4/VREF_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P Pin Number AA12 U12 V12 W12 Y12 XC2VP2 XC2VP4 XC2VP7
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L69N_5/VREF_5 IO_L69P_5 IO_L67N_5 IO_L67P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B
Y11 W11 V11 U11 AA11 Y10 V10 U10 W10 W9 V9 U9 Y8 W8 V8 Y7 W7 V7 V6 W6 W5
6 6 6 6 6 6 6 6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L05P_6 IO_L05N_6 IO_L06P_6
AB2 AA1 Y2 Y1 W2 W1 V4 V3 V2
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L06N_6 IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 Pin Number V1 U4 U3 U2 U1 U5 T5 T4 T3 T2 T1 R4 R3 R2 R1 R5 P6 P4 P3 P2 P1 P5 N5 N4 N3 N2 N1 N6 M6 M5 M4 M3 M2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP2 XC2VP4 XC2VP7
7 7 7
IO_L90P_7 IO_L90N_7 IO_L88P_7
L2 L3 L4
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L88N_7/VREF_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L43P_7 IO_L43N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 Pin Number L5 L6 K6 K1 K2 K3 K4 K5 J5 J1 J2 J3 J4 J6 H5 H1 H2 H3 H4 G1 G2 G3 G4 G5 F5 F1 F2 F3 F4 E1 E2 E3 E4 D1 D2 C1 C2
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XC2VP2
XC2VP4
XC2VP7
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2VP2 XC2VP4 XC2VP7
0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7
G9 G11 G10 F8 F7 G14 G13 G12 F16 F15 L16 K16 J16 H17 G17 T17 R17 P16 N16 M16 U16 U15 T14 T13 T12 U8 U7 T9 T11 T10 T6 R6 P7 N7 M7 L7
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank 7 7 7 7 Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number K7 J7 H6 G6 XC2VP2 XC2VP4 XC2VP7
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6
W20 B1 Y18 Y4 W3 Y5 B22 D3 D20 A21 Y19 A2 C18 C19 C4 C5 B4 B3 A3 A4 C6 A5 A6 B5 B6 B8 B7 A7 A8 C9 A9 A10
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NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 Pin Number B9 B10 B14 B13 A13 A14 C14 A15 A16 B15 B16 B18 B17 A17 A18 C17 A19 A20 B19 B20 AA20 AA19 AB20 AB19 Y17 AB18 AB17 AA17 AA18 AA16 AA15 AB16 AB15 Y14 AB14 AB13 AA13
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XC2VP2
XC2VP4
XC2VP7
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21 Pin Number AA14 AA10 AA9 AB10 AB9 Y9 AB8 AB7 AA7 AA8 AA6 AA5 AB6 AB5 Y6 AB4 AB3 AA3 AA4 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP2 XC2VP4 XC2VP7
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX
U6 U17 T8 T7 T16 T15 R7 R16 H7 H16 G8 G7 G16 G15 F6 F17 M22
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L1 B21 B2 AB11 AA21 AA2 A12 Y3 Y20 W4 W19 V5 V18 P9 P14 P13 P12 P11 P10 N9 N14 N13 N12 N11 N10 M9 M14 M13 M12 M11 M10 M1 L9 L22 L14 L13 L12
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XC2VP2
XC2VP4
XC2VP7
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Table 6: FG456/FGG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L11 L10 K9 K14 K13 K12 K11 K10 J9 J14 J13 J12 J11 J10 E5 E18 D4 D19 C3 C20 AB22 AB12 AB1 A22 A11 A1 XC2VP2 XC2VP4 XC2VP7
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 2: FG456/FGG456 Fine-Pitch BGA Package Specifications
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FG676/FGG676 Fine-Pitch BGA Package
As shown in Table 7, XC2VP20, XC2VP30, and XC2VP40 Virtex-II Pro devices are available in the FG676/FGG676 fine-pitch BGA package. The pins in these devices are the same, except for the differences shown in the "No Connects" column. Following this table are the FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 Pin Number E5 D5 E6 D6 G7 F7 E7 D7 C7 H8 G8 F8 E8 B8 A8 H9 G9 F9 E9 D9 C9 H10 H11 E10 E11 D10 C10 G11 F11 J12 H12 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L55N_0 IO_L55P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number G12 F12 E12 F13 D12 C12 J13 H13 E13 D13 C13 B13 XC2VP20 XC2VP30 XC2VP40
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L69N_1/VREF_1 IO_L69P_1 IO_L67N_1 IO_L67P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L46N_1 IO_L46P_1
B14 C14 D14 E14 H14 J14 C15 D15 F14 E15 F15 G15 H15 J15 F16 G16 C17 D17 E16 E17 H16 H17
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L45N_1/VREF_1 IO_L45P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L37N_1 IO_L37P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 Pin Number C18 D18 E18 F18 G18 H18 A19 B19 E19 F19 G19 H19 C20 D20 E20 F20 G20 D21 E21 D22 E22 XC2VP20 XC2VP30 XC2VP40
2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L24N_2 IO_L24P_2 IO_L31N_2
C25 C26 D25 D26 E23 F22 E25 E26 F21 G21 F23 F24 F25 NC NC
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L40N_2/VREF_2 IO_L40P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 Pin Number F26 G22 H22 G23 G24 G25 G26 H20 H21 H25 H26 J19 J20 J21 J22 J23 J24 J25 J26 K19 L19 K22 K23 K24 L24 K25 K26 L20 M20 L21 L22 L25 L26 M18 M19 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L58N_2/VREF_2 IO_L58P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L90N_2 IO_L90P_2 Pin Number M21 N21 M22 M23 M25 M26 N18 N19 N22 N23 N24 N25 XC2VP20 XC2VP30 XC2VP40
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L51N_3/VREF_3 IO_L51P_3
P25 P24 P23 P22 P19 P18 R26 R25 R23 R22 P21 R21 R19 R18 T26 T25 T22 T21 R20 T20 U26 U25
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L31N_3 IO_L31P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L03N_3/VREF_3 Pin Number T24 U24 U23 U22 T19 U19 V26 V25 V24 V23 V22 V21 V20 V19 W26 W25 W21 W20 Y26 Y25 Y24 Y23 W22 Y22 AA26 AA25 AA24 AA23 Y21 AA21 AB26 AB25 AA22 AB23 AC26 NC NC NC NC XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 3 3 3 3 3 Pin Description IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 Pin Number AC25 AC24 AD25 AD26 AE26 XC2VP20 XC2VP30 XC2VP40
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair
AB22 AC22 AB21 AC21 Y20 AA20 AB20 AC20 AD20 W19 Y19 AA19 AB19 AE19 AF19 W18 Y18 AA18 AB18 AC18 AD18 W17 W16 AB17 AB16 AC17 AD17 Y16 AA16
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P Pin Number V15 W15 Y15 AA15 AB15 AA14 AC15 AD15 V14 W14 AB14 AC14 AD14 AE14 XC2VP20 XC2VP30 XC2VP40
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L69N_5/VREF_5 IO_L69P_5 IO_L67N_5 IO_L67P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5
AE13 AD13 AC13 AB13 W13 V13 AD12 AC12 AA13 AB12 AA12 Y12 W12 V12 AA11 Y11 AD10 AC10 AB11 AB10
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L37N_5 IO_L37P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number W11 W10 AD9 AC9 AB9 AA9 Y9 W9 AF8 AE8 AB8 AA8 Y8 W8 AD7 AC7 AB7 AA7 Y7 AC6 AB6 AC5 AB5 XC2VP20 XC2VP30 XC2VP40
6 6 6 6 6 6 6 6 6 6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L23P_6
AE1 AD1 AD2 AC3 AC2 AC1 AB4 AA5 AB2 AB1 AA6 NC
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L31P_6 IO_L31N_6 IO_L33P_6 IO_L33N_6/VREF_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 Pin Number Y6 AA4 AA3 AA2 AA1 Y5 W5 Y4 Y3 Y2 Y1 W7 W6 W2 W1 V8 V7 V6 V5 V4 V3 V2 V1 U8 T8 U5 U4 U3 T3 U2 U1 T7 R7 T6 T5 XC2VP20 NC NC NC XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L55P_6 IO_L55N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 Pin Number T2 T1 R9 R8 R6 P6 R5 R4 R2 R1 P9 P8 P5 P4 P3 P2 XC2VP20 XC2VP30 XC2VP40
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
IO_L90P_7 IO_L90N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7
N2 N3 N4 N5 N8 N9 M1 M2 M4 M5 N6 M6 M8 M9 L1 L2 L5 L6
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L52P_7 IO_L52N_7/VREF_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L24P_7 IO_L24N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 Pin Number M7 L7 K1 K2 L3 K3 K4 K5 L8 K8 J1 J2 J3 J4 J5 J6 J7 J8 H1 H2 H6 H7 G1 G2 G3 G4 H5 G5 F1 F2 F3 F4 G6 F6 E1 NC NC XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 7 7 7 7 7 7 7 Pin Description IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 Pin Number E2 F5 E4 D1 D2 C1 C2 XC2VP20 XC2VP30 XC2VP40
0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3
C5 C8 D11 J10 J11 K12 K13 C19 C22 D16 J16 J17 K14 K15 E24 H24 K18 L18 L23 M17 N17 P17 R17 T18 T23 U18 W24
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6 6 6 7 7 7 7 7 7 7 Pin Description VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number AB24 U14 U15 V16 V17 AC16 AD19 AD22 U12 U13 V10 V11 AC11 AD5 AD8 P10 R10 T4 T9 U9 W3 AB3 E3 H3 K9 L4 L9 M10 N10 XC2VP20 XC2VP30 XC2VP40
N/A N/A N/A N/A N/A
PROG_B HSWAP_EN DXP DXN AVCCAUXTX4
B1 B3 A3 C4 B5
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 Pin Number B4 A4 A5 C6 A6 A7 B6 B7 B10 B9 A9 A10 C11 A11 A12 B11 B12 B16 B15 A15 A16 C16 A17 A18 B17 B18 B21 B20 A20 A21 C21 A22 A23 B22 B23 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description RSVD VBATT TMS TCK TDO CCLK PWRDWN_B DONE AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 Pin Number C23 A24 B24 B26 D24 AE24 AF24 AD23 AE23 AE22 AF23 AF22 AD21 AF21 AF20 AE20 AE21 AE18 AE17 AF18 AF17 AD16 AF16 AF15 AE15 AE16 AE12 AE11 AF12 AF11 AD11 AF10 AF9 AE9 AE10 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21 M2 M0 M1 TDI Pin Number AE7 AE6 AF7 AF6 AD6 AF5 AF4 AE4 AE5 AD4 AF3 AE3 D3 XC2VP20 XC2VP30 XC2VP40
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
G10 G13 G14 G17 J9 J18 K7 K10 K11 K16 K17 K20 L10 L17 N7 N20 P7 P20 T10 T17 U7
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND Pin Number U10 U11 U16 U17 U20 V9 V18 Y10 Y13 Y14 Y17 A2 A13 A14 A25 N1 N26 P1 P26 AF2 AF13 AF14 AF25 A1 A26 B2 B25 C3 C24 D4 D8 D19 D23 F10 F17 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number H4 H23 K6 K21 L11 L12 L13 L14 L15 L16 M3 M11 M12 M13 M14 M15 M16 M24 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R3 R11 R12 R13 R14 XC2VP20 XC2VP30 XC2VP40
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Table 7: FG676/FGG676 -- XC2VP20, XC2VP30, and XC2VP40 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number R15 R16 R24 T11 T12 T13 T14 T15 T16 U6 U21 W4 W23 AA10 AA17 AC4 AC8 AC19 AC23 AD3 AD24 AE2 AE25 AF1 AF26 XC2VP20 XC2VP30 XC2VP40
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 3: FG676/FGG676 Fine-Pitch BGA Package Specifications
DS083 (v4.7) November 5, 2007 Product Specification
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FF672 Flip-Chip Fine-Pitch BGA Package
As shown in Table 8, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FF672 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for differences shown in the "No Connects" column. Following this table are the FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number B24 A24 D21 C21 E20 D20 F19 E19 E18 D19 C19 B19 A19 G18 F18 D18 C18 G17 H16 F17 F16 E17 D17 G16 G15 E16 D16 F15 E15 D15 C15 H15 H14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP2 XC2VP4 XC2VP7
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number G14 F14 E14 D14 C14 B14 No Connects XC2VP2 XC2VP4 XC2VP7
Bank 0 0 0 0 0 0
Pin Description IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1
B13 C13 D13 E13 F13 G13 H13 H12 C12 D12 E12 F12 D11 E11 G12 G11 D10 E10 F11 F10 H11 G10 C9 D9 F9 G9 A8 B8 C8 D8
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NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number E9 E8 F8 D7 E7 C6 D6 A3 B3 No Connects XC2VP2 XC2VP4 XC2VP7
Bank 1 1 1 1 1 1 1 1 1
Pin Description IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L40N_2/VREF_2 IO_L40P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2
C4 D3 A2 B1 C2 C1 D2 D1 E4 E3 E2 E1 F5 F4 F3 F2 G6 G5 G4 G3 F1 G1 H6 H5 H4 H3 H2
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NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC
NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number H1 J7 J6 J5 J4 J3 J2 K6 K5 K4 K3 J1 K1 K7 L8 L7 M7 L6 L5 L4 L3 L2 L1 M8 N8 M6 M5 M4 M3 M2 M1 N7 N6 N5 N4 N3 N2
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No Connects XC2VP2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP4 XC2VP7
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Pin Description IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number No Connects XC2VP2 XC2VP4 XC2VP7
Bank
Pin Description
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3
P2 P3 P4 P5 P6 P7 R1 R2 R3 R4 R5 R6 P8 R8 T1 T2 T3 T4 T5 T6 R7 T7 T8 U7 U1 V1 U3 U4 U5 U6 V2 V3 V4 V5 V6 V7
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NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number W1 W2 W3 W4 W5 W6 Y1 AA1 Y3 Y4 Y5 Y6 AA2 AA3 AA4 AA5 AB1 AB2 AB3 AB4 AC1 AC2 AD1 AD2 AE1 AF2 AC3 AD4 AE3 AF3 No Connects XC2VP2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP4 XC2VP7
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Pin Description IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3
4 4 4 4 4 4
AC6 AD6 AB7 AC7 AA7 AA8
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number Y8 AB8 AB9 AC8 AD8 AE8 AF8 Y9 AA9 AC9 AD9 Y10 W11 AA10 AA11 AB10 AC10 Y11 Y12 AB11 AC11 AA12 AB12 AC12 AD12 W12 W13 Y13 AA13 AB13 AC13 AD13 AE13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP2 XC2VP4 XC2VP7
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Pin Description IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P
5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S
AE14 AD14 AC14
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number AB14 AA14 Y14 W14 W15 AD15 AC15 AB15 AA15 AC16 AB16 Y15 Y16 AC17 AB17 AA16 AA17 W16 Y17 AD18 AC18 AA18 Y18 AF19 AE19 AD19 AC19 AB18 AB19 Y19 AA19 AA20 AC20 AB20 AD21 AC21 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP2 XC2VP4 XC2VP7
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Pin Description IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number AF24 AE24 AD23 AC24 AE26 AF25 AD25 AD26 AC25 AC26 AB23 AB24 AB25 AB26 AA22 AA23 AA24 AA25 Y21 Y22 Y23 Y24 AA26 Y26 W21 W22 W23 W24 W25 W26 V20 V21 V22 V23 V24 V25 U21
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No Connects XC2VP2 XC2VP4 XC2VP7
Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
Pin Description IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number U22 U23 U24 V26 U26 U20 T19 T20 R20 T21 T22 T23 T24 T25 T26 R19 P19 R21 R22 R23 R24 R25 R26 P20 P21 P22 P23 P24 P25 No Connects XC2VP2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP4 XC2VP7
Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
Pin Description IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6
7 7 7 7 7 7 7
IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L87P_7
N25 N24 N23 N22 N21 N20 M26
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number M25 M24 M23 M22 M21 N19 M19 L26 L25 L24 L23 L22 L21 M20 L20 L19 K20 K26 J26 K24 K23 K22 K21 J25 J24 J23 J22 J21 J20 H26 H25 H24 H23 H22 H21 G26 F26
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No Connects XC2VP2 XC2VP4 XC2VP7
Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Pin Description IO_L87N_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7 IO_L45N_7
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number G24 G23 G22 G21 F25 F24 F23 F22 E26 E25 E24 E23 D26 D25 C26 C25 B26 A25 D24 C23 No Connects XC2VP2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP4 XC2VP7
Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Pin Description IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7
0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2
C17 C20 H17 H18 J14 J15 J16 C7 H9 C10 H10 J11 J12 J13 G2 J8
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number K2 K8 L9 M9 N9 P9 R9 T9 U2 U8 V8 Y2 W9 AD7 V11 V12 V13 W10 AD10 V14 V15 V16 W17 W18 AD17 AD20 P18 R18 T18 U19 U25 V19 Y25 G25 J19 K19 K25
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No Connects XC2VP2 XC2VP4 XC2VP7
Bank 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6 6 6 7 7 7 7
Pin Description VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number L18 M18 N18 No Connects XC2VP2 XC2VP4 XC2VP7
Bank 7 7 7
Pin Description VCCO_7 VCCO_7 VCCO_7
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9
W7 D22 AB6 AC22 W20 AB21 G8 H20 H7 F7 AC5 E21 D5 E6 F20 G19 B11 B12 A12 A11 C11 A10 A9 B10 B9 B6 B7 A7 A6 C5 A5 A4 B5
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NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number B4 AE4 AE5 AF4 AF5 AD5 AF6 AF7 AE7 AE6 AE9 AE10 AF9 AF10 AD11 AF11 AF12 AE12 AE11 B22 B23 A23 A22 C22 A21 A20 B21 B20 B17 B18 A18 A17 C16 A16 A15 B16 B15
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No Connects XC2VP2 NC NC NC NC NC NC NC NC NC NC XC2VP4 NC NC NC NC NC NC NC NC NC NC XC2VP7
Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pin Description AVCCAUXRX9 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6
NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number AE15 AE16 AF15 AF16 AD16 AF17 AF18 AE18 AE17 AE20 AE21 AF20 AF21 AD22 AF22 AF23 AE23 AE22 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP2 XC2VP4 XC2VP7
Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pin Description AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
H8 J9 K9 U9 V9 W8 H19 J10 J17 J18 K11 K16 K18 L10 L17 T10 T17 U11
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number U16 U18 V10 V17 V18 W19 B2 N1 P1 A13 A14 AE2 B25 N26 P26 AE25 AF13 AF14 C3 D4 E5 F6 G7 Y7 AA6 AB5 AC4 AD3 C24 D23 E22 F21 G20 K10 K12 K13 K14
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No Connects XC2VP2 XC2VP4 XC2VP7
Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number K15 K17 L11 L12 L13 L14 L15 L16 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14
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No Connects XC2VP2 XC2VP4 XC2VP7
Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 Pin Number R15 R16 R17 T11 T12 T13 T14 T15 T16 U10 U12 U13 U14 U15 U17 Y20 AA21 AB22 AC23 AD24 No Connects XC2VP2 XC2VP4 XC2VP7
Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 4: FF672 Flip-Chip Fine-Pitch BGA Package Specifications
FF896 Flip-Chip Fine-Pitch BGA Package
As shown in Table 9, XC2VP7, XC2VP20, and XC2VP30 Virtex-II Pro devices are available in the FF896 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for differences shown in the "No Connects" column. Following this table are the FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Virtex-II Pro devices IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair
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No Connects XC2VPX20 (if Different) Pin Number E25 E24 F24 F23 E23 E22 G23 H22 G22 F22 F21 D24 C24 H21 G21 E21 D21 D23 C23 H20 G20 E20 D20 B23 A23 H19 G19 E19 E18 C22 B22 F20 F19 G17 F17 B21 NC NC NC NC NC NC NC NC NC XC2VP7 XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Virtex-II Pro devices IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S BREFCLKN BREFCLKP XC2VPX20 (if Different) Pin Number A21 H18 G18 C21 C20 J17 H17 E17 D17 D18 C18 J16 H16 E16 D16 C16 B16 G16 F16 XC2VP7 NC NC NC NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L56N_1 IO_L56P_1
F15 G15 B15 C15 D15 E15 H15 J15 C13 D13 D14 E14 H14 J14 C11 C10 NC NC NC NC
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Virtex-II Pro devices IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 XC2VPX20 (if Different) Pin Number G13 H13 A10 B10 F14 G14 F12 F11 B9 C9 E13 E12 G12 H12 A8 B8 D11 E11 G11 H11 C8 D8 D10 E10 G10 H10 C7 D7 F10 F9 G9 H9 G8 E9 E8 F8 XC2VP7 NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 1 1 1 Virtex-II Pro devices IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 XC2VPX20 (if Different) Pin Number F7 E7 E6 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2 IO_L40P_2
A3 B3 G6 G5 C5 D5 C2 C1 J8 J7 C4 D3 D2 D1 H6 H5 E4 E3 E2 E1 K8 K7 F4 F3 F2 F1 J6 J5 G4 G3 G2 G1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro devices IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 XC2VPX20 (if Different) Pin Number L8 L7 H4 H3 H2 J2 M8 M7 K6 K5 J1 K1 M6 M5 J4 J3 K2 L2 N8 N7 K4 K3 L1 M1 N6 N5 L5 L4 M2 N2 P9 R9 M4 M3 N1 P1 XC2VP7 NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro devices IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 XC2VPX20 (if Different) Pin Number P8 P7 N4 N3 P3 P2 R8 R7 P5 P4 R2 T2 R6 R5 R4 R3 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3
U1 V1 T5 T6 T3 T4 U2 U3 T7 T8 U4 U5 V2 W2 T9 U9 V3 V4 W1
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro devices IO_L57P_3 IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 XC2VPX20 (if Different) Pin Number Y1 U7 U8 V5 V6 Y2 AA2 V7 V8 W3 W4 AA1 AB1 W5 W6 Y4 Y5 AA3 AA4 W7 W8 AB3 AB4 AB2 AC2 AA5 AA6 AC3 AC4 AD1 AD2 Y7 Y8 AB5 AB6 AE1 NC NC NC NC NC NC NC XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro devices IO_L39P_3 IO_L38N_3 IO_L38P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 XC2VPX20 (if Different) Pin Number AE2 AA7 AA8 AD3 AD4 AF1 AF2 AC5 AC6 AF3 AF4 AE3 AE4 AB7 AB8 AE5 AF6 AG1 AG2 AD5 AD6 AG3 AH4 AH1 AH2 AG5 AH5 AJ3 AK3 XC2VP7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
4 4 4 4 4 4
AG6 AF7 AC9 AD9 AG7 AH7
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Virtex-II Pro devices IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 XC2VPX20 (if Different) Pin Number AD8 AG8 AH8 AC10 AD10 AE7 AE8 AJ8 AK8 AC11 AD11 AF8 AF9 AF10 AG10 AC12 AD12 AE9 AE10 AH9 AJ9 AC13 AD13 AE11 AE12 AH10 AH11 AB14 AC14 AF11 AG11 AJ10 AK10 AF12 AF13 AG13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 Virtex-II Pro devices IO_L57P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P XC2VPX20 (if Different) Pin Number AH13 AB15 AC15 AD14 AE14 AF14 AG14 AD15 AE15 AF15 AG15 AH15 AJ15 XC2VP7 NC No Connects XC2VP20, XC2VPX20 XC2VP30
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5
BREFCLKN BREFCLKP
AJ16 AH16 AG16 AF16 AE16 AD16 AG17 AF17 AE17 AD17 AC16 AB16 AH18 AG18 AF18 AF19 AK21 AJ21 AG20 AF20 AC17 AB17 NC NC NC NC NC NC NC NC NC NC
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Virtex-II Pro devices IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B XC2VPX20 (if Different) Pin Number AH20 AH21 AE19 AE20 AD18 AC18 AJ22 AH22 AE21 AE22 AD19 AC19 AG21 AF21 AF22 AF23 AD20 AC20 AK23 AJ23 AE23 AE24 AD21 AC21 AH23 AG23 AD23 AH24 AG24 AD22 AC22 AF24 AG25 XC2VP7 NC NC NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6
AK28 AJ28
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro devices IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6 IO_L33N_6/VREF_6 IO_L34P_6 IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 XC2VPX20 (if Different) Pin Number AH26 AG26 AH29 AH30 AH27 AG28 AD25 AD26 AG29 AG30 AF25 AE26 AB23 AB24 AE27 AE28 AF27 AF28 AC25 AC26 AF29 AF30 AD27 AD28 AA23 AA24 AE29 AE30 AB25 AB26 Y23 Y24 AD29 AD30 AC27 AC28 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro devices IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 XC2VPX20 (if Different) Pin Number AA25 AA26 AC29 AB29 AB27 AB28 W23 W24 AA27 AA28 Y26 Y27 W25 W26 AB30 AA30 W27 W28 V23 V24 AA29 Y29 V25 V26 U23 U24 Y30 W30 V27 V28 U22 T22 W29 V29 U26 U27 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro devices IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 XC2VPX20 (if Different) Pin Number T23 T24 U28 U29 T27 T28 T25 T26 V30 U30 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L87P_7 IO_L87N_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7
R28 R27 R26 R25 T29 R29 P27 P26 R24 R23 P29 P28 N28 N27 P24 P23 P30 N30 M28 M27 R22 P22 N29 M29 L27
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro devices IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 XC2VPX20 (if Different) Pin Number L26 N26 N25 M30 L30 K28 K27 N24 N23 L29 K29 J28 J27 M26 M25 K30 J30 K26 K25 M24 M23 J29 H29 H28 H27 L24 L23 G30 G29 G28 G27 J26 J25 F30 F29 F28 NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro devices IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 XC2VPX20 (if Different) Pin Number F27 K24 K23 E30 E29 E28 E27 H26 H25 D30 D29 D28 C27 J24 J23 C30 C29 D26 C26 G26 G25 B28 A28 XC2VP7 NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20, XC2VPX20 XC2VP30
0 0 0 0 0 0 0 0 0 0 1 1
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1
K21 K20 K19 K18 K17 K16 J21 J20 J19 J18 K15 K14
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Virtex-II Pro devices VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 XC2VPX20 (if Different) Pin Number K13 K12 K11 K10 J13 J12 J11 J10 R10 P10 N10 N9 M10 M9 L10 L9 K9 J9 AB9 AA9 Y10 Y9 W10 W9 V10 V9 U10 T10 AB13 AB12 AB11 AB10 AA15 AA14 AA13 AA12 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro devices VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 XC2VPX20 (if Different) Pin Number AA11 AA10 AB21 AB20 AB19 AB18 AA21 AA20 AA19 AA18 AA17 AA16 AB22 AA22 Y22 Y21 W22 W21 V22 V21 U21 T21 R21 P21 N22 N21 M22 M21 L22 L21 K22 J22 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
N/A N/A N/A
CCLK PROG_B DONE
AC7 G24 AC8
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 XC2VPX20 (if Different) Pin Number AD24 AC24 AC23 G7 F26 F5 H8 AD7 H23 D6 H7 H24 D25 B26 B27 A27 A26 C25 A25 A24 B25 B24 B19 B20 A20 A19 C19 A18 A17 B18 B17 B13 B14 A14 A13 C12 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 XC2VPX20 (if Different) Pin Number A12 A11 B12 B11 B6 B7 A7 A6 C6 A5 A4 B5 B4 AJ4 AJ5 AK4 AK5 AH6 AK6 AK7 AJ7 AJ6 AJ11 AJ12 AK11 AK12 AH12 AK13 AK14 AJ14 AJ13 AJ17 AJ18 AK17 AK18 AH19 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21 XC2VPX20 (if Different) Pin Number AK19 AK20 AJ20 AJ19 AJ24 AJ25 AK24 AK25 AH25 AK26 AK27 AJ27 AJ26 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
AK29 AK16 AK15 AK2 AJ30 AJ1 T30 T1 R30 R1 B30 B1 A29 A16 A15 A2 Y19 Y18 Y17 Y16 Y15 Y14
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND XC2VPX20 (if Different) Pin Number Y13 Y12 W20 W11 V20 V11 U20 U11 T20 T11 R20 R11 P20 P11 N20 N11 M20 M11 L19 L18 L17 L16 L15 L14 L13 L12 AK22 AK9 AJ29 AJ2 AH28 AH17 AH14 AH3 AG27 AG22 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX20 (if Different) Pin Number AG19 AG12 AG9 AG4 AF26 AF5 AE25 AE18 AE13 AE6 AC30 AC1 Y28 Y25 Y20 Y11 Y6 Y3 W19 W18 W17 W16 W15 W14 W13 W12 V19 V18 V17 V16 V15 V14 V13 V12 U25 U19 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX20 (if Different) Pin Number U18 U17 U16 U15 U14 U13 U12 U6 T19 T18 T17 T16 T15 T14 T13 T12 R19 R18 R17 R16 R15 R14 R13 R12 P25 P19 P18 P17 P16 P15 P14 P13 P12 P6 N19 N18 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX20 (if Different) Pin Number N17 N16 N15 N14 N13 N12 M19 M18 M17 M16 M15 M14 M13 M12 L28 L25 L20 L11 L6 L3 H30 H1 F25 F18 F13 F6 E26 E5 D27 D22 D19 D12 D9 D4 C28 C17 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
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Table 9: FF896 -- XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank N/A N/A N/A N/A N/A N/A Virtex-II Pro devices GND GND GND GND GND GND XC2VPX20 (if Different) Pin Number C14 C3 B29 B2 A22 A9 XC2VP7 No Connects XC2VP20, XC2VPX20 XC2VP30
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 5: FF896 Flip-Chip Fine-Pitch BGA Package Specifications
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FF1152 Flip-Chip Fine-Pitch BGA Package
As shown in Table 10, XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Virtex-II Pro devices are available in the FF1152 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the differences shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 Pin Number E29 E28 H26 G26 H25 G25 J25 K24 J24 F26 E26 D30 D29 K23 J23 F24 E24 D28 C28 H24 G24 G23 F23 E27 D27 K22 J22 H22 G22 D26 C26 K21 J21 F22 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Pin Description IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L55N_0 IO_L55P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S Pin Number E22 E25 D25 H21 G21 D22 D23 D24 C24 K20 J20 F21 E21 C21 C22 L19 K19 G20 F20 D21 D20 J19 H19 G19 F19 E19 D19 L18 K18 G18 F18 E18 D18 J18 H18 H17 J17 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L56N_1 IO_L56P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 Pin Number D17 E17 F17 G17 K17 L17 D16 E16 F16 G16 H16 J16 D15 D14 F15 G15 K16 L16 C13 C14 E14 F14 J15 K15 C11 D11 D12 D13 G14 H14 D10 E10 E13 F13 J14 K14 C9 D9 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Pin Description IO_L37N_1 IO_L37P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L21N_1 IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 Pin Number G13 H13 J13 K13 D8 E8 F12 G12 G11 H11 C7 D7 E11 F11 J12 K12 D6 D5 E9 F9 J11 K11 J10 G10 H10 G9 H9 E7 E6 D2 D1 F8 F7 E4 E3 E2 E1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 101
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L15N_2 IO_L15P_2 IO_L16N_2/VREF_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L18N_2 IO_L18P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22N_2/VREF_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 Pin Number J8 J7 F5 F4 G4 G3 G6 G5 F2 F1 L10 L9 H6 H5 G2 G1 J6 J5 J4 J3 K8 K7 H4 H3 H2 H1 M10 M9 K5 K4 J2 K2 L8 L7 L6 L5 K1 L1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 102
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2 IO_L40P_2 IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 Pin Number N10 N9 M7 M6 L2 M2 N8 N7 L4 L3 M4 M3 P10 P9 N6 N5 M1 N1 P8 P7 N4 N3 N2 P2 R10 R9 P6 P5 P4 P3 T11 U11 R7 R6 P1 R1 T10 T9 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 103
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 Pin Number R4 R3 R2 T2 T8 T7 T6 T5 T4 T3 U10 U9 U6 U5 U2 V2 U8 U7 U4 U3 V3 V4 V7 V8 V5 V6 W2 Y2 V9 V10 W3 W4 Y1 AA1 V11 W11 W5 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 104
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 Pin Number W6 Y3 Y4 W7 W8 Y6 Y7 AA2 AB2 W9 W10 AA3 AA4 AB1 AC1 Y9 Y10 AA5 AA6 AB3 AB4 AA7 AA8 AB5 AB6 AC2 AD2 AA9 AA10 AC3 AC4 AD1 AE1 AB7 AB8 AC6 AC7 AD3 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 105
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L39P_3 IO_L38N_3 IO_L38P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 IO_L18N_3 IO_L18P_3 IO_L17N_3 IO_L17P_3 IO_L16N_3 IO_L16P_3 IO_L15N_3/VREF_3 IO_L15P_3 IO_L06N_3 Pin Number AD4 AB9 AB10 AD5 AD6 AE2 AF2 AD7 AD8 AE4 AE5 AG1 AG2 AC9 AC10 AF3 AF4 AH1 AH2 AE7 AE8 AF5 AF6 AG3 AG4 AD9 AD10 AH3 AH4 AJ1 AJ2 AF7 AF8 AK1 AK2 AG5 AG6 AL1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 106
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4 IO_L26P_4 IO_L27N_4 Pin Number AL2 AG7 AH8 AH5 AH6 AK3 AK4 AJ7 AJ8 AJ4 AJ5 AL5 AL6 AG9 AH9 AK6 AK7 AF10 AL7 AM7 AE11 AF11 AG10 AH10 AK8 AL8 AE12 AF12 AJ9 AK9 AL9 AM9 AG11 AH11 AH12 AJ12 AK10 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 107
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L27P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 Pin Number AL10 AE13 AF13 AG13 AH13 AJ11 AK11 AE14 AF14 AJ13 AK13 AL11 AM11 AE15 AF15 AG14 AH14 AL13 AL12 AD16 AE16 AJ14 AK14 AM14 AM13 AF16 AG16 AH15 AJ15 AL14 AL15 AD17 AE17 AH16 AJ16 AK16 AL16 AF17 No Connects XC2VP20 NC XC2VP30 NC XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 108
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 Pin Number AG17 AH17 AJ17 AK17 AL17 AL18 AK18 AJ18 AH18 AG18 AF18 AL19 AK19 AJ19 AH19 AE18 AD18 AL20 AL21 AJ20 AH20 AG19 AF19 AM22 AM21 AK21 AJ21 AE19 AD19 AL23 AL22 AH21 AG21 AF20 AE20 AM24 AL24 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 109
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L21N_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 IO_L19P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number AK22 AJ22 AF21 AE21 AK24 AJ24 AH22 AG22 AF22 AE22 AL25 AK25 AJ23 AH23 AH24 AG24 AM26 AL26 AK26 AJ26 AF23 AE23 AL27 AK27 AH25 AG25 AF24 AE24 AM28 AL28 AF25 AK28 AK29 AH26 AG26 AL29 AL30 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 110
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L15P_6 IO_L15N_6/VREF_6 IO_L16P_6 IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6 IO_L33N_6/VREF_6 Pin Number AJ30 AJ31 AJ27 AJ28 AK31 AK32 AH29 AH30 AH27 AG28 AL33 AL34 AG29 AG30 AK33 AK34 AF27 AF28 AJ33 AJ34 AH31 AH32 AD25 AD26 AG31 AG32 AF29 AF30 AE27 AE28 AH33 AH34 AF31 AF32 AC25 AC26 AG33 AG34 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 111
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L34P_6 IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 Pin Number AE30 AE31 AD27 AD28 AF33 AE33 AD29 AD30 AB25 AB26 AD31 AD32 AC28 AC29 AB27 AB28 AE34 AD34 AC31 AC32 AA25 AA26 AD33 AC33 AB29 AB30 AA27 AA28 AB31 AB32 AA29 AA30 Y25 Y26 AC34 AB34 AA31 AA32 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 112
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 Pin Description IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L87P_7 IO_L87N_7 IO_L86P_7 Pin Number W25 W26 AB33 AA33 Y28 Y29 W27 W28 Y31 Y32 W29 W30 W24 V24 AA34 Y34 W31 W32 V25 V26 Y33 W33 V29 V30 V27 V28 V31 V32 U32 U31 U28 U27 V33 U33 U30 U29 U26 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 113
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 Pin Number U25 T32 T31 T30 T29 T28 T27 T33 R33 R32 R31 T26 T25 R34 P34 R29 R28 U24 T24 P32 P31 P30 P29 R26 R25 P33 N33 N32 N31 P28 P27 N34 M34 N30 N29 P26 P25 M32 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 114
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7/VREF_7 IO_L21P_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L18P_7 Pin Number M31 L32 L31 N28 N27 M33 L33 M29 M28 N26 N25 L34 K34 L30 L29 L28 L27 K33 J33 K31 K30 M26 M25 H34 H33 H32 H31 K28 K27 J32 J31 J30 J29 G34 G33 H30 H29 L26 NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 115
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Pin Description IO_L18N_7 IO_L17P_7 IO_L17N_7 IO_L16P_7 IO_L16N_7/VREF_7 IO_L15P_7 IO_L15N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 Pin Number L25 F34 F33 G30 G29 G32 G31 F31 F30 J28 J27 E34 E33 E32 E31 F28 F27 D34 D33 C29 E20 F25 L20 L21 L22 L23 M18 M19 M20 M21 M22 C6 E15 F10 L12 L13 L14 No Connects XC2VP20 NC NC NC NC NC NC NC XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Pin Description VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 Pin Number L15 M13 M14 M15 M16 M17 F3 K6 M11 N11 N12 P11 P12 R5 R11 R12 T12 U12 V12 W12 Y5 Y11 Y12 AA11 AA12 AB11 AB12 AC11 AE6 AJ3 AC13 AC14 AC15 AC16 AC17 AD12 AD13 AD14 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 Pin Description VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number AD15 AJ10 AK15 AM6 AC18 AC19 AC20 AC21 AC22 AD20 AD21 AD22 AD23 AJ25 AK20 AM29 V23 W23 Y23 Y24 Y30 AA23 AA24 AB23 AB24 AC24 AE29 AJ32 F32 K29 M24 N23 N24 P23 P24 R23 R24 R30 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank 7 7 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCO_7 VCCO_7 CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX2 VTTXPAD2 TXNPAD2 TXPPAD2 GNDA2 RXPPAD2 RXNPAD2 VTRXPAD2 AVCCAUXRX2 AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX5 Pin Number T23 U23 AE9 J26 AE10 AF26 AE26 AE25 J9 H28 H7 K10 AF9 K25 G8 K9 K26 G27 B32 B33 A33 A32 C30 A31 A30 B31 B30 B28 B29 A29 A28 C27 A27 A26 B27 B26 B24 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VTTXPAD5 TXNPAD5 TXPPAD5 GNDA5 RXPPAD5 RXNPAD5 VTRXPAD5 AVCCAUXRX5 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX8 VTTXPAD8 TXNPAD8 TXPPAD8 GNDA8 RXPPAD8 RXNPAD8 VTRXPAD8 AVCCAUXRX8 AVCCAUXTX9 VTTXPAD9 TXNPAD9 Pin Number B25 A25 A24 C23 A23 A22 B23 B22 B20 B21 A21 A20 C20 A19 A18 B19 B18 B16 B17 A17 A16 C15 A15 A14 B15 B14 B12 B13 A13 A12 C12 A11 A10 B11 B10 B8 B9 A9 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 NC NC NC NC NC NC NC NC XC2VP30 NC NC NC NC NC NC NC NC XC2VP40 NC NC NC NC NC NC NC NC XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 AVCCAUXTX11 VTTXPAD11 TXNPAD11 TXPPAD11 GNDA11 RXPPAD11 RXNPAD11 VTRXPAD11 AVCCAUXRX11 AVCCAUXRX14 VTRXPAD14 RXNPAD14 RXPPAD14 GNDA14 TXPPAD14 TXNPAD14 VTTXPAD14 AVCCAUXTX14 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX17 VTRXPAD17 RXNPAD17 RXPPAD17 GNDA17 Pin Number A8 C8 A7 A6 B7 B6 B4 B5 A5 A4 C5 A3 A2 B3 B2 AN2 AN3 AP2 AP3 AM5 AP4 AP5 AN5 AN4 AN6 AN7 AP6 AP7 AM8 AP8 AP9 AN9 AN8 AN10 AN11 AP10 AP11 AM12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description TXPPAD17 TXNPAD17 VTTXPAD17 AVCCAUXTX17 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX20 VTRXPAD20 RXNPAD20 RXPPAD20 GNDA20 TXPPAD20 TXNPAD20 VTTXPAD20 AVCCAUXTX20 AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 Pin Number AP12 AP13 AN13 AN12 AN14 AN15 AP14 AP15 AM15 AP16 AP17 AN17 AN16 AN18 AN19 AP18 AP19 AM20 AP20 AP21 AN21 AN20 AN22 AN23 AP22 AP23 AM23 AP24 AP25 AN25 AN24 AN26 AN27 AP26 AP27 AM27 AP28 AP29 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 NC NC NC NC XC2VP30 NC NC NC NC XC2VP40 NC NC NC NC XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VTTXPAD21 AVCCAUXTX21 AVCCAUXRX23 VTRXPAD23 RXNPAD23 RXPPAD23 GNDA23 TXPPAD23 TXNPAD23 VTTXPAD23 AVCCAUXTX23 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number AN29 AN28 AN30 AN31 AP30 AP31 AM30 AP32 AP33 AN33 AN32 L11 L24 M12 M23 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P13 P22 R13 R22 T13 T22 U13 U22 V13 V22 W13 W22 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX Pin Number Y13 Y22 AA13 AA22 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AC12 AC23 AD11 AD24 C3 C4 C17 C18 C31 C32 D3 D32 U1 V1 U34 V34 AL3 AL32 AM3 AM4 AM17 AM18 AM31 AM32 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AF34 B34 C1 C2 C10 C16 C19 C25 C33 C34 D4 D31 E5 E12 E23 E30 F6 F29 G7 G28 B1 H8 H12 H15 H20 J1 H27 AF1 K3 K32 M5 M8 M27 M30 P14 P15 P16 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number P17 P18 P19 P20 P21 R8 R14 R15 R16 R17 R18 R19 R20 R21 R27 T1 T14 T15 T16 T17 T18 T19 T20 T21 T34 U14 U15 U16 U17 U18 U19 U20 U21 V14 V15 V16 V17 V18 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number V19 V20 V21 W1 W14 W15 W16 W17 W18 W19 W20 W21 W34 Y8 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y27 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AC5 AC8 AC27 AC30 AE3 AE32 H23 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
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Table 10: FF1152 -- XC2VP20, XC2VP30, XC2VP40, and XC2VP50 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AG8 AG12 AG15 AG20 AG23 AG27 J34 AH7 AH28 AJ6 AJ29 AK5 AK12 AK23 AK30 AL4 AL31 AM1 AM2 AM10 AM16 AM19 AM25 AM33 AM34 AN1 AN34 No Connects XC2VP20 XC2VP30 XC2VP40 XC2VP50
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 6: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications
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FF1148 Flip-Chip Fine-Pitch BGA Package
As shown in Table 11, XC2VP40 and XC2VP50 Virtex-II Pro devices are available in the FF1148 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the differences shown in the No Connect column. Following this table are the FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 Pin Number E25 F25 J24 K24 C25 D25 G25 A25 B25 G24 G23 H23 H22 E24 F24 C24 C23 J23 K23 A24 B24 E23 F23 K22 L22 D23 D22 A23 B23 J21 J20 F22 G22 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L55N_0 IO_L55P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L66N_0 IO_L66P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number B22 C22 K21 L21 G21 H21 E21 F21 K20 L20 C21 D21 A21 B21 G20 H19 E20 F20 C20 D19 K19 L19 A20 B20 F19 G19 B19 C19 H18 J18 F18 G18 D18 E18 K18 L18 B18 C18 NC NC XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L66N_1/VREF_1 IO_L66P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L56N_1 IO_L56P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 Pin Number C17 B17 L17 K17 E17 D17 G17 F17 J17 H17 C16 B16 G16 F16 B15 A15 L16 K16 D16 C15 F15 E15 H16 G15 B14 A14 D14 C14 L15 K15 F14 E14 H14 G14 L14 K14 C13 NC NC XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 Pin Description IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L21N_1 IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 Pin Number B13 G13 F13 J15 J14 B12 A12 D13 D12 L13 K13 F12 E12 B11 A11 K12 J12 C12 C11 F11 E11 H13 H12 G12 G11 B10 A10 G10 D10 C10 K11 J11 F10 E10 B8 B9 C9 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 IO_L07P_2 IO_L08N_2 IO_L08P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2/VREF_2 IO_L10P_2 IO_L11N_2 IO_L11P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2 IO_L13P_2 IO_L14N_2 IO_L14P_2 IO_L15N_2 IO_L15P_2 IO_L16N_2/VREF_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L18N_2 IO_L18P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 Pin Number D9 B7 A7 B6 A6 E8 D8 B4 A4 B3 A3 H7 H8 C6 C7 C5 B5 K8 J8 C1 C2 E7 D7 J6 J7 D5 D6 E4 D4 L9 K9 E3 D3 D1 D2 K7 L7 F6 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L21P_2 IO_L22N_2/VREF_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L26N_2 IO_L26P_2 IO_L27N_2 IO_L27P_2 IO_L28N_2/VREF_2 IO_L28P_2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2 Pin Number E6 F7 F8 M10 L10 G5 F5 F3 F4 M8 M9 F1 F2 G6 G7 M7 N8 G3 H4 G1 G2 N10 N11 H5 H6 H2 H3 N6 N7 K4 J4 J2 J3 P10 P11 K5 K6 L3 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 135
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L40P_2 IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L59N_2 Pin Number K3 R9 P9 K1 K2 L5 L6 P7 P8 L1 L2 M5 M6 R10 R11 M3 M4 M1 M2 R7 T8 P4 N4 N2 N3 T10 T11 P5 P6 R3 P3 T6 T7 P1 P2 R5 R6 U10 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 136
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L56N_3 IO_L56P_3 Pin Number U11 R1 R2 T3 T4 U8 U9 U2 T2 U4 U5 U6 U7 V3 U3 V6 V7 V10 V11 V4 V5 V2 W2 V8 V9 W6 W7 W3 W4 W10 W11 Y5 Y6 Y3 AA3 W8 Y7 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 137
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L38N_3 IO_L38P_3 IO_L37N_3 IO_L37P_3 Pin Number Y1 Y2 AA5 AA6 Y10 Y11 AA4 AB4 AA1 AA2 Y9 AA9 AB6 AB7 AB2 AB3 AA10 AA11 AC5 AC6 AC3 AC4 AA7 AA8 AC1 AC2 AD5 AD6 AB10 AB11 AD3 AE3 AD1 AD2 AB8 AC7 AE5 AE6 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 138
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L30N_3 IO_L30P_3 IO_L29N_3 IO_L29P_3 IO_L28N_3 IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L26N_3 IO_L26P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 IO_L18N_3 IO_L18P_3 Pin Number AE4 AF4 AC10 AD10 AE1 AE2 AF6 AF7 AC8 AC9 AF2 AF3 AG5 AG6 AD9 AE9 AG4 AH3 AG2 AG3 AD7 AE7 AH6 AH7 AH5 AJ5 AE8 AF8 AH1 AH2 AJ6 AK6 AG7 AG8 AJ3 AJ4 AJ1 AJ2 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 139
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 Pin Description IO_L17N_3 IO_L17P_3 IO_L16N_3 IO_L16P_3 IO_L15N_3/VREF_3 IO_L15P_3 IO_L14N_3 IO_L14P_3 IO_L13N_3 IO_L13P_3 IO_L12N_3 IO_L12P_3 IO_L11N_3 IO_L11P_3 IO_L10N_3 IO_L10P_3 IO_L09N_3/VREF_3 IO_L09P_3 IO_L08N_3 IO_L08P_3 IO_L07N_3 IO_L07P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) Pin Number AH9 AJ9 AK7 AL7 AK4 AL4 AJ7 AJ8 AK3 AL3 AL5 AL6 AK8 AL8 AL1 AL2 AM6 AM7 AL9 AM9 AM5 AN5 AM1 AM2 AN8 AN9 AN6 AP6 AN4 AP4 AN7 AP7 AN3 AP3 AK10 AJ10 AF11 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 140
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4 IO_L26P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 Pin Number AE11 AM10 AL10 AH10 AP10 AN10 AH11 AH12 AG12 AG13 AK11 AJ11 AM11 AM12 AF12 AE12 AP11 AN11 AK12 AJ12 AE13 AD13 AL12 AL13 AP12 AN12 AF14 AF15 AJ13 AH13 AN13 AM13 AE14 AD14 AH14 AG14 AK14 AJ14 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 141
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 Pin Description IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L66N_4 IO_L66P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 Pin Number AE15 AD15 AM14 AL14 AP14 AN14 AH15 AG16 AK15 AJ15 AM15 AL16 AE16 AD16 AP15 AN15 AJ16 AH16 AN16 AM16 AG17 AF17 AJ17 AH17 AL17 AK17 AE17 AD17 AN17 AM17 AM18 AN18 AD18 AE18 AK18 AL18 AH18 NC NC XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 142
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L66N_5/VREF_5 IO_L66P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L27N_5/VREF_5 Pin Number AJ18 AF18 AG18 AM19 AN19 AH19 AJ19 AN20 AP20 AD19 AE19 AL19 AM20 AJ20 AK20 AG19 AH20 AN21 AP21 AL21 AM21 AD20 AE20 AJ21 AK21 AG21 AH21 AD21 AE21 AM22 AN22 AH22 AJ22 AF20 AF21 AN23 AP23 AL22 NC NC XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 143
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L21N_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 IO_L19P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 Pin Number AL23 AD22 AE22 AJ23 AK23 AN24 AP24 AE23 AF23 AM23 AM24 AJ24 AK24 AG22 AG23 AH23 AH24 AN25 AP25 AH25 AL25 AM25 AE24 AF24 AJ25 AK25 AP32 AN32 AP28 AN28 AP31 AN31 AP29 AN29 AN26 AN27 AM33 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 144
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L06N_6 IO_L07P_6 IO_L07N_6 IO_L08P_6 IO_L08N_6 IO_L09P_6 IO_L09N_6/VREF_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6/VREF_6 IO_L16P_6 IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 Pin Number AM34 AN30 AM30 AM26 AL26 AM28 AM29 AL33 AL34 AL27 AK27 AL29 AL30 AL32 AK32 AJ27 AJ28 AL31 AK31 AL28 AK28 AJ26 AH26 AJ33 AJ34 AJ31 AJ32 AG27 AG28 AK29 AJ29 AH33 AH34 AF27 AE27 AJ30 AH30 AH28 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 145
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L25N_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6 IO_L33N_6/VREF_6 IO_L34P_6 IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 Pin Number AH29 AE28 AD28 AG32 AG33 AH32 AG31 AE26 AD26 AG29 AG30 AF32 AF33 AC26 AC27 AF28 AF29 AE33 AE34 AD25 AC25 AF31 AE31 AE29 AE30 AC28 AB27 AD33 AD34 AE32 AD32 AB24 AB25 AD29 AD30 AC33 AC34 AA27 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 146
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 Pin Number AA28 AC31 AC32 AC29 AC30 AA24 AA25 AB32 AB33 AB28 AB29 AA26 Y26 AA33 AA34 AB31 AA31 Y24 Y25 AA29 AA30 Y33 Y34 Y28 W27 AA32 Y32 Y29 Y30 W24 W25 W31 W32 W28 W29 V26 V27 W33 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 147
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L87P_7 IO_L87N_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 Pin Number V33 V30 V31 V24 V25 V28 V29 U32 V32 U28 U29 U30 U31 T33 U33 U26 U27 T31 T32 R33 R34 U24 U25 R29 R30 P33 P34 T28 T29 P32 R32 P29 P30 T24 T25 N32 N33 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 148
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 Pin Number N31 P31 T27 R28 M33 M34 M31 M32 R24 R25 M29 M30 L33 L34 P27 P28 L29 L30 K33 K34 P26 R26 K32 L32 K29 K30 P24 P25 J32 J33 J31 K31 N28 N29 H32 H33 H29 H30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 149
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L30P_7 IO_L30N_7 IO_L29P_7 IO_L29N_7 IO_L28P_7 IO_L28N_7/VREF_7 IO_L27P_7 IO_L27N_7 IO_L26P_7 IO_L26N_7 IO_L25P_7 IO_L25N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7/VREF_7 IO_L21P_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L18P_7 IO_L18N_7 IO_L17P_7 IO_L17N_7 IO_L16P_7 IO_L16N_7/VREF_7 IO_L15P_7 IO_L15N_7 IO_L14P_7 IO_L14N_7 Pin Number N24 N25 G33 G34 H31 G32 N27 M28 G28 G29 F33 F34 M26 M27 F31 F32 F30 G30 L25 M25 F27 F28 E29 F29 L28 K28 D33 D34 D32 E32 K26 L26 D31 E31 D29 D30 J28 J29 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L13P_7 IO_L13N_7 IO_L12P_7 IO_L12N_7 IO_L11P_7 IO_L11N_7 IO_L10P_7 IO_L10N_7/VREF_7 IO_L09P_7 IO_L09N_7 IO_L08P_7 IO_L08N_7 IO_L07P_7 IO_L07N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 Pin Number D28 E28 C33 C34 J27 K27 B30 C30 C28 C29 H27 H28 A32 B32 A31 B31 D27 E27 A29 B29 A28 B28 D26 C26 B26 B27 E33 R31 L31 G31 C31 R27 L27 G27 C27 J26 M24 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 Pin Number U23 T23 R23 P23 N23 AK33 AM31 AH31 AD31 Y31 AM27 AH27 AD27 Y27 AF26 AC24 AB23 AA23 Y23 W23 V23 AL24 AG24 AD23 AC22 AC21 AL20 AG20 AC20 AC19 AC18 AC17 AC16 AL15 AG15 AC15 AC14 AC13 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 Pin Description VCCO_4 VCCO_4 VCCO_4 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_1 VCCO_1 VCCO_1 Pin Number AD12 AL11 AG11 AB12 AA12 Y12 W12 V12 AC11 AF9 AM8 AH8 AD8 Y8 AM4 AH4 AD4 Y4 AK2 U12 T12 R12 P12 N12 M11 J9 R8 L8 G8 C8 R4 L4 G4 C4 E2 M17 M16 M15 XC2VP40 XC2VP50
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN VCCINT VCCINT VCCINT Pin Number H15 D15 M14 M13 L12 H11 D11 H24 D24 L23 M22 M21 M20 H20 D20 M19 M18 AG9 G26 AF10 AG25 AG26 AF25 G9 F26 F9 H10 AG10 H25 H9 J10 J25 H26 AD24 L24 AC23 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Pin Number M23 AB22 AA22 Y22 W22 V22 U22 T22 R22 P22 N22 AB21 N21 AB20 N20 AB19 N19 AB18 N18 AB17 N17 AB16 N16 AB15 N15 AB14 N14 AB13 AA13 Y13 W13 V13 U13 T13 R13 P13 N13 AC12 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number M12 AD11 L11 AN34 AG34 U34 H34 B34 AP33 A33 AP27 A27 AP17 A17 AP8 A8 AP2 A2 AN1 AG1 U1 H1 B1 AK34 AF34 AB34 W34 V34 T34 N34 J34 E34 AN33 B33 AM32 C32 AP30 AK30 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AF30 AB30 W30 T30 N30 J30 E30 A30 AP26 AK26 AB26 W26 T26 N26 E26 A26 AE25 K25 AP22 AK22 AF22 J22 E22 A22 Y21 W21 V21 U21 T21 R21 AA20 Y20 W20 V20 U20 T20 R20 P20 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AP19 AK19 AF19 AA19 Y19 W19 V19 U19 T19 R19 P19 J19 E19 A19 AP18 AA18 Y18 W18 V18 U18 T18 R18 P18 A18 AA17 Y17 W17 V17 U17 T17 R17 P17 AP16 AK16 AF16 AA16 Y16 W16 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number V16 U16 T16 R16 P16 J16 E16 A16 AA15 Y15 W15 V15 U15 T15 R15 P15 Y14 W14 V14 U14 T14 R14 AP13 AK13 AF13 J13 E13 A13 AE10 K10 AP9 AK9 AB9 W9 T9 N9 E9 A9 XC2VP40 XC2VP50
DS083 (v4.7) November 5, 2007 Product Specification
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Table 11: FF1148 -- XC2VP40 and XC2VP50 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AP5 AK5 AF5 AB5 W5 T5 N5 J5 E5 A5 AM3 C3 AN2 B2 AK1 AF1 AB1 W1 V1 T1 N1 J1 E1 XC2VP40 XC2VP50
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
DS083 (v4.7) November 5, 2007 Product Specification
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FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 7: FF1148 Flip-Chip Fine-Pitch BGA Package Specifications
DS083 (v4.7) November 5, 2007 Product Specification
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FF1517 Flip-Chip Fine-Pitch BGA Package
As shown in Table 12, XC2VP50 and XC2VP70 Virtex-II Pro devices are available in the FF1517 flip-chip fine-pitch BGA package. Following this table are the FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L34N_0 Pin Number D31 E31 K30 J30 G30 H30 K28 E30 F30 C30 D30 J29 K29 G29 H29 E29 F29 L28 L27 C29 D29 H28 J28 M27 M26 D28 E28 H27 J27 J26 K26 F28 G27 D27 NC NC NC NC NC NC NC No Connects XC2VP50 XC2VP70
DS083 (v4.7) November 5, 2007 Product Specification
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L34P_0 IO_L35N_0 IO_L35P_0 IO_L36N_0 IO_L36P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L55N_0 IO_L55P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L58N_0 IO_L58P_0 IO_L59N_0
Pin Number E27 L26 L25 G26 H26 E26 F26 K25 K24 C26 D26 H25 J25 M25 M24 F25 G25 C25 D25 L23 M22 H24 J24 E25 E24 N23 M23 H23 J23 F24 G23 K22 L22 C23 D23 H22 J22 N22
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No Connects XC2VP50 NC NC NC NC NC XC2VP70
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L59P_0 IO_L60N_0 IO_L60P_0 IO_L64N_0 IO_L64P_0 IO_L65N_0 IO_L65P_0 IO_L66N_0 IO_L66P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L66N_1/VREF_1 IO_L66P_1 IO_L65N_1 IO_L65P_1
Pin Number N21 E23 F22 D22 E22 H21 H20 G22 G21 D21 E21 J21 K21 C22 C21 F21 F20 L21 M21 D20 E20 K20 J20 N20 M20 E19 D19 G19 F19 L19 K19 J19 H19 C19 C18 N19 M19
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No Connects XC2VP50 XC2VP70
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L64N_1 IO_L64P_1 IO_L60N_1 IO_L60P_1 IO_L59N_1 IO_L59P_1 IO_L58N_1 IO_L58P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L56N_1 IO_L56P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1
Pin Number E18 D18 G18 F18 L18 K18 J18 H18 D17 C17 N18 M18 E17 E16 G17 F16 J17 H17 J16 H16 D15 C15 L17 K16 F15 E15 H15 G15 N17 M17 D14 C14 F14 E14 M16 M15 H14 G14
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No Connects XC2VP50 XC2VP70
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L36N_1/VREF_1 IO_L36P_1 IO_L35N_1 IO_L35P_1 IO_L34N_1 IO_L34P_1 IO_L30N_1 IO_L30P_1 IO_L29N_1 IO_L29P_1 IO_L28N_1 IO_L28P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L21N_1 IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 Pin Number E13 D13 K15 J15 G13 F12 J13 H13 L15 L14 E12 D12 J12 H12 K14 J14 D11 C11 F11 E11 M14 M13 H11 G11 J11 J10 L13 L12 D10 C10 F10 E10 K10 H10 G10 K12 K11 E9
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No Connects XC2VP50 NC NC NC NC NC NC NC NC NC NC NC NC XC2VP70
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L01P_1/VRN_1 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L73N_2 IO_L73P_2 IO_L75N_2 IO_L75P_2 IO_L76N_2/VREF_2 IO_L76P_2 IO_L78N_2 IO_L78P_2 IO_L79N_2 IO_L79P_2 IO_L81N_2 IO_L81P_2 IO_L82N_2/VREF_2 IO_L82P_2 IO_L84N_2 IO_L84P_2 IO_L07N_2 IO_L07P_2 IO_L08N_2 IO_L08P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2/VREF_2 IO_L10P_2
Pin Number D9 C7 D7 G9 H9 C5 D5 D6 E6 H8 J9 E7 F7 D1 D2 E2 E3 F5 G5 F3 F4 F1 F2 G6 G7 G3 G4 G1 G2 H6 H7 K8 K9 H2 H3 J6 J7
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No Connects XC2VP50 XC2VP70
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L11N_2 IO_L11P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2 IO_L13P_2 IO_L14N_2 IO_L14P_2 IO_L15N_2 IO_L15P_2 IO_L16N_2/VREF_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L18N_2 IO_L18P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22N_2/VREF_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L26N_2 IO_L26P_2 IO_L27N_2 IO_L27P_2 IO_L28N_2/VREF_2 IO_L28P_2 IO_L29N_2 IO_L29P_2
Pin Number L9 M10 H4 J5 J1 J2 M8 N9 K6 K7 K4 K5 P10 N10 K3 J3 K1 K2 M11 N11 L7 L8 L5 L6 P8 P9 L3 L4 L1 L2 P11 P12 M6 M7 M2 M3 R9 R10
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No Connects XC2VP50 XC2VP70
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Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L30N_2 IO_L30P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2 IO_L40P_2 IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2
Pin Number N6 N7 M4 N5 R11 R12 N1 N2 P6 P7 R13 T13 P4 P5 P3 N3 T10 T11 P1 P2 R7 R8 T12 U12 R5 R6 R3 R4 U8 T8 R1 R2 T6 T7 U9 U10 T2 T3
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No Connects XC2VP50 XC2VP70
Module 4 of 4 169
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 IO_L90N_3
Pin Number U5 U6 U13 V13 U4 T4 U1 U2 V9 V10 V7 V8 V5 V6 V11 V12 V3 V4 V1 V2 W10 W11 W7 W8 W5 W6 W12 W13 W3 W4 Y7 Y8 W9 Y9 Y3 Y4 AA7
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No Connects XC2VP50 XC2VP70
Module 4 of 4 170
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3
Pin Number AA8 Y11 Y12 AA5 AA6 AA3 AA4 Y13 AA13 AB7 AB8 AB5 AB6 AA9 AA10 AB3 AB4 AB1 AB2 AA11 AA12 AC5 AC6 AC1 AC2 AB9 AB10 AC8 AD8 AC4 AD4 AB11 AB12 AD6 AD7 AD2 AD3 AC9
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No Connects XC2VP50 XC2VP70
Module 4 of 4 171
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L38N_3 IO_L38P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L30N_3 IO_L30P_3 IO_L29N_3 IO_L29P_3 IO_L28N_3
Pin Number AC10 AE7 AE8 AE5 AE6 AB13 AC13 AE3 AE4 AE1 AE2 AD10 AD11 AF6 AF7 AF4 AF5 AC12 AD12 AF1 AF2 AG6 AG7 AE9 AE10 AF3 AG3 AG1 AG2 AE11 AE12 AH6 AH7 AG5 AH4 AD13 AE13 AH2
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No Connects XC2VP50 XC2VP70
Module 4 of 4 172
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L26N_3 IO_L26P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 IO_L18N_3 IO_L18P_3 IO_L17N_3 IO_L17P_3 IO_L16N_3 IO_L16P_3 IO_L15N_3/VREF_3 IO_L15P_3 IO_L14N_3 IO_L14P_3 IO_L13N_3 IO_L13P_3 IO_L12N_3 IO_L12P_3 IO_L11N_3 IO_L11P_3 IO_L10N_3 IO_L10P_3 IO_L09N_3/VREF_3 Pin Number AH3 AJ7 AJ8 AF8 AF9 AJ5 AJ6 AJ3 AJ4 AF10 AG10 AJ1 AJ2 AK6 AK7 AF11 AF12 AK4 AK5 AK1 AK2 AG9 AH8 AL6 AL7 AK3 AL3 AG11 AH11 AL1 AL2 AM6 AM7 AH10 AJ9 AL5 AM4 AM2
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Module 4 of 4 173
No Connects XC2VP50 XC2VP70
DS083 (v4.7) November 5, 2007 Product Specification
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L09P_3 IO_L08N_3 IO_L08P_3 IO_L07N_3 IO_L07P_3 IO_L84N_3 IO_L84P_3 IO_L82N_3 IO_L82P_3 IO_L81N_3/VREF_3 IO_L81P_3 IO_L79N_3 IO_L79P_3 IO_L78N_3 IO_L78P_3 IO_L76N_3 IO_L76P_3 IO_L75N_3/VREF_3 IO_L75P_3 IO_L73N_3 IO_L73P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1
Pin Number AM3 AK8 AK9 AN6 AN7 AN3 AN4 AN1 AN2 AN5 AP5 AP3 AP4 AP1 AP2 AR2 AR3 AT1 AT2 AT5 AU5 AR6 AT6 AL9 AM8 AP7 AR7 AM9 AN9 AR8 AT8 AT7 AU7 AT9 AR9 AK11 AK12
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No Connects XC2VP50 XC2VP70
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Module 4 of 4 174
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4 IO_L26P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L28N_4 IO_L28P_4 IO_L29N_4 IO_L29P_4 IO_L30N_4 IO_L30P_4 IO_L34N_4 IO_L34P_4 IO_L35N_4 IO_L35P_4 IO_L36N_4 IO_L36P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4
Pin Number AN10 AM10 AK10 AR10 AP10 AU10 AT10 AJ12 AJ13 AL10 AL11 AN11 AM11 AH13 AH14 AR11 AP11 AU11 AT11 AL14 AK14 AM12 AL12 AT12 AR12 AJ14 AJ15 AM13 AL13 AP12 AN13 AL15 AK15 AT13 AR13 AN14 AM14 AH15
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No Connects XC2VP50 XC2VP70
NC NC NC NC NC NC NC NC NC NC NC NC
Module 4 of 4 175
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L58N_4 IO_L58P_4 IO_L59N_4 IO_L59P_4 IO_L60N_4 IO_L60P_4 IO_L64N_4 IO_L64P_4 IO_L65N_4 IO_L65P_4 IO_L66N_4
Pin Number AH16 AR14 AP14 AU14 AT14 AH17 AG17 AN15 AM15 AR15 AP15 AK16 AJ17 AU15 AT15 AM16 AL16 AM17 AL17 AP16 AN17 AR16 AR17 AH18 AG18 AU17 AT17 AM18 AL18 AK18 AJ18 AP18 AN18 AT18 AR18 AH19 AG19 AU18
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No Connects XC2VP50 XC2VP70
Module 4 of 4 176
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L66P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L66N_5/VREF_5 IO_L66P_5 IO_L65N_5 IO_L65P_5 IO_L64N_5 IO_L64P_5 IO_L60N_5 IO_L60P_5 IO_L59N_5 IO_L59P_5 IO_L58N_5 IO_L58P_5
Pin Number AU19 AM19 AL19 AK19 AJ19 AP19 AN19 AT19 AR19 AH20 AG20 AL20 AK20 AR20 AT20 AH21 AJ21 AP20 AP21 AU21 AU22 AK21 AL21 AR21 AT21 AN21 AN22 AM20 AM21 AR22 AT22 AP22 AR23 AG21 AG22 AL22 AM22
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No Connects XC2VP50 XC2VP70
Module 4 of 4 177
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L36N_5/VREF_5 IO_L36P_5 IO_L35N_5 IO_L35P_5 IO_L34N_5 IO_L34P_5 IO_L30N_5 IO_L30P_5
Pin Number AT23 AU23 AJ22 AK22 AN23 AP24 AL23 AM23 AH23 AG23 AR24 AR25 AL24 AM24 AH22 AJ23 AT25 AU25 AN25 AP25 AH24 AH25 AL25 AM25 AT26 AU26 AK24 AK25 AP26 AR26 AM26 AN26 AJ25 AJ26 AR27 AT27 AN27 AP28
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No Connects XC2VP50 XC2VP70
NC NC NC NC NC NC NC NC
Module 4 of 4 178
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 Pin Description IO_L29N_5 IO_L29P_5 IO_L28N_5 IO_L28P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L21N_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 IO_L19P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 Pin Number AK26 AL26 AL27 AM27 AR28 AT28 AH26 AH27 AL28 AM28 AT29 AU29 AJ27 AJ28 AP29 AR29 AM29 AN29 AK29 AL29 AT30 AU30 AP30 AR30 AK28 AM30 AN30 AL30 AK30 AR31 AT31 AU33 AT33 AT32 AR32 AN31 AM31
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Module 4 of 4 179
No Connects XC2VP50 NC NC NC NC XC2VP70
DS083 (v4.7) November 5, 2007 Product Specification
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L73P_6 IO_L73N_6 IO_L75P_6 IO_L75N_6/VREF_6 IO_L76P_6 IO_L76N_6 IO_L78P_6 IO_L78N_6 IO_L79P_6 IO_L79N_6 IO_L81P_6 IO_L81N_6/VREF_6 IO_L82P_6 IO_L82N_6 IO_L84P_6 IO_L84N_6 IO_L07P_6 IO_L07N_6 IO_L08P_6 IO_L08N_6 IO_L09P_6 IO_L09N_6/VREF_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6
Pin Number AR33 AP33 AM32 AL31 AT34 AR34 AU35 AT35 AT38 AT39 AR37 AR38 AP38 AP39 AP36 AP37 AP35 AN35 AN38 AN39 AN36 AN37 AN33 AN34 AK31 AK32 AM37 AM38 AM36 AL35 AJ31 AH30 AM33 AM34 AL38 AL39 AH29 AG29
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No Connects XC2VP50 XC2VP70
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Module 4 of 4 180
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L15P_6 IO_L15N_6/VREF_6 IO_L16P_6 IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 IO_L25N_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6 IO_L33N_6/VREF_6 Pin Number AL37 AK37 AL33 AL34 AH32 AG31 AK38 AK39 AK35 AK36 AF28 AF29 AK33 AK34 AJ38 AJ39 AG30 AF30 AJ36 AJ37 AJ34 AJ35 AF31 AF32 AJ32 AJ33 AH37 AH38 AE27 AD27 AH36 AG35 AH33 AH34 AE28 AE29 AG38 AG39
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Module 4 of 4 181
No Connects XC2VP50 XC2VP70
DS083 (v4.7) November 5, 2007 Product Specification
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L34P_6 IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 IO_L52N_6
Pin Number AG37 AF37 AE30 AE31 AG33 AG34 AF38 AF39 AD28 AC28 AF35 AF36 AF33 AF34 AD29 AD30 AE38 AE39 AE36 AE37 AC27 AB27 AE34 AE35 AE32 AE33 AC30 AC31 AD37 AD38 AD33 AD34 AB28 AB29 AD36 AC36 AD32 AC32
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No Connects XC2VP50 XC2VP70
Module 4 of 4 182
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L87P_7 IO_L87N_7 IO_L86P_7
Pin Number AB30 AB31 AC38 AC39 AC34 AC35 AA28 AA29 AB38 AB39 AB36 AB37 AA30 AA31 AB34 AB35 AB32 AB33 AA27 Y27 AA36 AA37 AA34 AA35 Y28 Y29 AA32 AA33 Y36 Y37 Y31 W31 Y32 Y33 W36 W37 W27
www.xilinx.com
No Connects XC2VP50 XC2VP70
Module 4 of 4 183
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7
Pin Number W28 W34 W35 W32 W33 W29 W30 V38 V39 V36 V37 V28 V29 V34 V35 V32 V33 V30 V31 U38 U39 T36 U36 V27 U27 U34 U35 T37 T38 U30 U31 T33 T34 R38 R39 T32 U32 R36
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No Connects XC2VP50 XC2VP70
Module 4 of 4 184
R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L30P_7 IO_L30N_7 IO_L29P_7 IO_L29N_7 IO_L28P_7 IO_L28N_7/VREF_7 IO_L27P_7 IO_L27N_7 IO_L26P_7 IO_L26N_7 IO_L25P_7 IO_L25N_7 IO_L24P_7
Pin Number R37 R34 R35 U28 T28 R32 R33 P38 P39 T29 T30 N37 P37 P35 P36 T27 R27 P33 P34 N38 N39 R28 R29 N35 M36 N33 N34 R30 R31 M37 M38 M33 M34 P28 P29 L38 L39 L36
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No Connects XC2VP50 XC2VP70
Module 4 of 4 185
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7/VREF_7 IO_L21P_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L18P_7 IO_L18N_7 IO_L17P_7 IO_L17N_7 IO_L16P_7 IO_L16N_7/VREF_7 IO_L15P_7 IO_L15N_7 IO_L14P_7 IO_L14N_7 IO_L13P_7 IO_L13N_7 IO_L12P_7 IO_L12N_7 IO_L11P_7 IO_L11N_7 IO_L10P_7 IO_L10N_7/VREF_7 IO_L09P_7 IO_L09N_7 IO_L08P_7 IO_L08N_7 IO_L07P_7 IO_L07N_7 IO_L84P_7 IO_L84N_7 IO_L82P_7
Pin Number L37 P31 P32 L34 L35 L32 L33 N29 M29 K38 K39 J37 K37 N30 P30 K35 K36 K34 K33 N31 M32 J38 J39 J35 H36 M30 L31 J33 J34 H37 H38 K31 K32 H33 H34 G38 G39 G36
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No Connects XC2VP50 XC2VP70
NC NC NC
Module 4 of 4 186
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L82N_7/VREF_7 IO_L81P_7 IO_L81N_7 IO_L79P_7 IO_L79N_7 IO_L78P_7 IO_L78N_7 IO_L76P_7 IO_L76N_7/VREF_7 IO_L75P_7 IO_L75N_7 IO_L73P_7 IO_L73N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7
Pin Number G37 G33 G34 F38 F39 F36 F37 G35 F35 E37 E38 D38 D39 F33 E33 J31 H32 E34 D34 D35 C35 H31 G31 D33 C33 E39 U37 N36 J36 E36 Y35 U33 N32 J32 F32 U29 N28
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No Connects XC2VP50 NC NC NC NC NC NC NC NC NC NC NC NC NC XC2VP70
Module 4 of 4 187
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 4 4
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_4 VCCO_4
Pin Number P27 W26 V26 U26 T26 R26 AR39 AC37 AR36 AL36 AG36 AC33 AP32 AL32 AG32 AC29 AG28 AF27 AE26 AD26 AC26 AB26 AA26 Y26 AP27 AK27 AG26 AG25 AF25 AG24 AF24 AP23 AK23 AF23 AF22 AF21 AF19 AF18
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No Connects XC2VP50 XC2VP70
Module 4 of 4 188
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2
Pin Number AP17 AK17 AF17 AG16 AF16 AG15 AF15 AG14 AP13 AK13 AE14 AD14 AC14 AB14 AA14 Y14 AF13 AG12 AC11 AP8 AL8 AG8 AC7 AR4 AL4 AG4 AC3 AR1 W14 V14 U14 T14 R14 P13 N12 U11 N8 J8
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No Connects XC2VP50 XC2VP70
Module 4 of 4 189
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 CCLK PROG_B DONE M0 M1
Pin Number F8 U7 Y5 N4 J4 E4 U3 E1 N14 K13 F13 P19 P18 P17 K17 F17 P16 N16 P15 N15 K27 F27 N26 P25 N25 P24 N24 P23 K23 F23 P22 P21 AJ10 D32 AJ11 AP31 AJ30
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No Connects XC2VP50 XC2VP70
Module 4 of 4 190
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX2 VTTXPAD2 TXNPAD2 TXPPAD2 GNDA2 RXPPAD2 RXNPAD2 VTRXPAD2 AVCCAUXRX2 AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX5 VTTXPAD5 TXNPAD5 TXPPAD5 GNDA5 RXPPAD5 RXNPAD5 VTRXPAD5 AVCCAUXRX5
Pin Number AJ29 E8 L30 L10 F9 AP9 E32 D8 L11 L29 F31 B35 B36 A36 A35 C34 A34 A33 B34 B33 B31 B32 A32 A31 C31 A30 A29 B30 B29 B27 B28 A28 A27 C27 A26 A25 B26 B25
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No Connects XC2VP50 XC2VP70
Module 4 of 4 191
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX8 VTTXPAD8 TXNPAD8 TXPPAD8 GNDA8 RXPPAD8 RXNPAD8 VTRXPAD8 AVCCAUXRX8 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 AVCCAUXTX11 VTTXPAD11
Pin Number B23 B24 A24 A23 C24 A22 A21 B22 B21 B18 B19 A19 A18 C16 A17 A16 B17 B16 B14 B15 A15 A14 C13 A13 A12 B13 B12 B10 B11 A11 A10 C9 A9 A8 B9 B8 B6 B7
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No Connects XC2VP50 XC2VP70
Module 4 of 4 192
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description TXNPAD11 TXPPAD11 GNDA11 RXPPAD11 RXNPAD11 VTRXPAD11 AVCCAUXRX11 AVCCAUXRX14 VTRXPAD14 RXNPAD14 RXPPAD14 GNDA14 TXPPAD14 TXNPAD14 VTTXPAD14 AVCCAUXTX14 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX17 VTRXPAD17 RXNPAD17 RXPPAD17 GNDA17 TXPPAD17 TXNPAD17 VTTXPAD17 AVCCAUXTX17 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18
Pin Number A7 A6 C6 A5 A4 B5 B4 AV4 AV5 AW4 AW5 AU6 AW6 AW7 AV7 AV6 AV8 AV9 AW8 AW9 AU9 AW10 AW11 AV11 AV10 AV12 AV13 AW12 AW13 AU13 AW14 AW15 AV15 AV14 AV16 AV17 AW16 AW17
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No Connects XC2VP50 XC2VP70
Module 4 of 4 193
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX20 VTRXPAD20 RXNPAD20 RXPPAD20 GNDA20 TXPPAD20 TXNPAD20 VTTXPAD20 AVCCAUXTX20 AVCCAUXRX21 VTRXPAD21 RXNPAD21 RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21 AVCCAUXRX23 VTRXPAD23 RXNPAD23 RXPPAD23 GNDA23 TXPPAD23
Pin Number AU16 AW18 AW19 AV19 AV18 AV21 AV22 AW21 AW22 AU24 AW23 AW24 AV24 AV23 AV25 AV26 AW25 AW26 AU27 AW27 AW28 AV28 AV27 AV29 AV30 AW29 AW30 AU31 AW31 AW32 AV32 AV31 AV33 AV34 AW33 AW34 AU34 AW35
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No Connects XC2VP50 XC2VP70
Module 4 of 4 194
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description TXNPAD23 VTTXPAD23 AVCCAUXTX23 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
Pin Number AW36 AV36 AV35 AH28 M28 AG27 N27 AF26 P26 AE25 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AE24 AD24 T24 R24 AE23 R23 AE22 R22 AE21 R21 AE20 R20 AE19 R19 AE18 R18 AE17
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No Connects XC2VP50 XC2VP70
Module 4 of 4 195
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX
Pin Number R17 AE16 AD16 T16 R16 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 AF14 P14 AG13 N13 AH12 M12 AV39 AA39 Y39 W39 B39 AW38 Y38 A38 AR35 E35 AP34 F34 AW20 AV20 B20 A20
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No Connects XC2VP50 XC2VP70
Module 4 of 4 196
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin Number AP6 F6 AR5 E5 AW2 Y2 A2 AV1 AA1 Y1 W1 B1 A3 AV2 AU2 AA2 W2 C2 B2 AU1 AM1 AH1 AD1 T1 M1 H1 C1 AD5 T5 M5 H5 AU4 AT4 D4 C4 AW3 AV3
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No Connects XC2VP50 XC2VP70
Module 4 of 4 197
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin Number AU3 AT3 D3 C3 B3 AN12 G12 C12 Y10 AH9 AD9 T9 M9 AU8 AN8 G8 C8 Y6 AM5 AH5 T17 AT16 AN16 AJ16 AC16 AB16 AA16 Y16 W16 V16 U16 L16 G16 D16 AU12 AB18 AA18 Y18
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No Connects XC2VP50 XC2VP70
Module 4 of 4 198
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin Number W18 V18 U18 T18 AD17 AC17 AB17 AA17 Y17 W17 V17 U17 P20 L20 G20 C20 AD19 AC19 AB19 AA19 Y19 W19 V19 U19 T19 AD18 AC18 U21 T21 AU20 AN20 AJ20 AF20 AD20 AC20 AB20 AA20 Y20
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No Connects XC2VP50 XC2VP70
Module 4 of 4 199
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin Number W20 V20 U20 T20 AC22 AB22 AA22 Y22 W22 V22 U22 T22 AD21 AC21 AB21 AA21 Y21 W21 V21 B38 AW37 AV37 AU37 AT37 D37 C37 B37 A37 AU36 AT36 D36 C36 AM35 AH35 AD35 T35 M35 H35
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No Connects XC2VP50 XC2VP70
Module 4 of 4 200
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin Number Y34 AU32 AN32 G32 C32 AH31 AD31 T31 M31 Y30 AU28 AN28 G28 C28 AT24 AN24 AJ24 AC24 AB24 AA24 Y24 W24 V24 U24 L24 G24 D24 AD23 AC23 AB23 AA23 Y23 W23 V23 U23 T23 AD22 AU39
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No Connects XC2VP50 XC2VP70
Module 4 of 4 201
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 12: FF1517 -- XC2VP50 and XC2VP70 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AM39 AH39 AD39 T39 M39 H39 C39 AV38 AU38 AA38 W38 C38 No Connects XC2VP50 XC2VP70
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 202
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 8: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 203
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FF1704 Flip-Chip Fine-Pitch BGA Package
As shown in Table 13, XC2VP70 and XC2VP100 Virtex-II Pro devices are available in the FF1704 flip-chip fine-pitch BGA package. Following this table are the FF1704 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Virtex-II Pro Devices IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 XC2VPX70 (if Different) Pin Number G34 H34 F34 E34 C34 D34 K32 H33 J33 F33 G33 E33 D33 H32 J32 E32 F32 C33 C32 K31 L31 H31 J31 G31 F31 D31 E31 L30 M30 J30 K30 G30 H30 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
Module 4 of 4 204
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Virtex-II Pro Devices IO_L34N_0 IO_L34P_0 IO_L35N_0 IO_L35P_0 IO_L36N_0 IO_L36P_0/VREF_0 IO_L78N_0 IO_L78P_0 IO_L83_0/No_Pair IO_L84N_0 IO_L84P_0 IO_L85N_0 IO_L85P_0 IO_L86N_0 IO_L86P_0 IO_L87N_0 IO_L87P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 XC2VPX70 (if Different) Pin Number E30 F30 D30 C30 M28 M29 K29 L29 H29 F29 G29 D29 E29 L28 K28 H28 J28 E28 F28 C29 C28 L27 M27 J27 K27 H27 G27 E27 F27 M25 M26 L26 K26 H26 J26 F26 NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP70, XC2VPX70 XC2VP100
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Virtex-II Pro Devices IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L55N_0 IO_L55P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L58N_0 IO_L58P_0 IO_L59N_0 IO_L59P_0 IO_L60N_0 IO_L60P_0 IO_L64N_0 IO_L64P_0 IO_L65N_0 IO_L65P_0 IO_L66N_0 IO_L66P_0/VREF_0 IO_L67N_0 IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S BREFCLKN BREFCLKP XC2VPX70 (if Different) Pin Number G26 D27 D26 K25 L25 G25 H25 E26 E25 C25 C26 L24 M24 J24 K24 G24 H24 E24 F24 D24 C24 M22 M23 K23 L23 J23 H23 E23 F23 C23 D23 K22 J22 F22 G22 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Virtex-II Pro Devices IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L66N_1/VREF_1 IO_L66P_1 IO_L65N_1 IO_L65P_1 IO_L64N_1 IO_L64P_1 IO_L60N_1 IO_L60P_1 IO_L59N_1 IO_L59P_1 IO_L58N_1 IO_L58P_1 IO_L57N_1/VREF_1 IO_L57P_1 IO_L56N_1 IO_L56P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 XC2VPX70 (if Different) Pin Number G21 F21 J21 K21 D20 C20 F20 E20 H20 J20 L20 K20 M20 M21 C19 D19 F19 E19 H19 G19 K19 J19 M19 L19 C17 C18 E18 E17 H18 G18 L18 K18 D17 D16 G17 F17 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Virtex-II Pro Devices IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1 IO_L87N_1/VREF_1 IO_L87P_1 IO_L86N_1 IO_L86P_1 IO_L85N_1 IO_L85P_1 IO_L84N_1 IO_L84P_1 IO_L83_1/No_Pair IO_L78N_1 IO_L78P_1 IO_L36N_1/VREF_1 IO_L36P_1 IO_L35N_1 IO_L35P_1 IO_L34N_1 IO_L34P_1 IO_L30N_1 XC2VPX70 (if Different) Pin Number J17 H17 K17 L17 M17 M18 F16 E16 G16 H16 K16 J16 M16 L16 C15 C14 F15 E15 J15 H15 K15 L15 E14 D14 G14 F14 H14 L14 K14 M14 M15 C13 D13 F13 E13 H13 NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Virtex-II Pro Devices IO_L30P_1 IO_L29N_1 IO_L29P_1 IO_L28N_1 IO_L28P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L21N_1 IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 XC2VPX70 (if Different) Pin Number G13 K13 J13 M13 L13 E12 D12 F12 G12 J12 H12 L12 K12 C11 C10 F11 E11 J11 H11 D10 E10 G10 F10 J10 H10 K11 D9 C9 E9 F9 H9 G9 No Connects XC2VP70, XC2VPX70 XC2VP100
2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2
C5 C6 E7
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro Devices IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L73N_2 IO_L73P_2 IO_L74N_2 IO_L74P_2 IO_L75N_2 IO_L75P_2 IO_L76N_2/VREF_2 IO_L76P_2 IO_L77N_2 IO_L77P_2 IO_L78N_2 IO_L78P_2 IO_L79N_2 IO_L79P_2 IO_L80N_2 IO_L80P_2 IO_L81N_2 IO_L81P_2 IO_L82N_2/VREF_2 IO_L82P_2 IO_L83N_2 IO_L83P_2 IO_L84N_2 IO_L84P_2 IO_L07N_2 IO_L07P_2 IO_L08N_2 XC2VPX70 (if Different) Pin Number D7 E6 D6 G6 F7 D3 E3 D1 D2 E1 E2 F4 F3 F1 F2 G3 G4 G2 G1 G5 H6 H4 H5 H3 H2 H7 J8 J6 J7 J5 J4 J1 J2 K9 L10 K6 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro Devices IO_L08P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2/VREF_2 IO_L10P_2 IO_L11N_2 IO_L11P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2 IO_L13P_2 IO_L14N_2 IO_L14P_2 IO_L15N_2 IO_L15P_2 IO_L16N_2/VREF_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L18N_2 IO_L18P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22N_2/VREF_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L26N_2 XC2VPX70 (if Different) Pin Number K5 K8 K7 K2 K1 L8 L9 L6 L7 K3 L3 L5 L4 L1 L2 M7 M8 M11 M12 M9 M10 M2 M3 M4 M5 N7 N8 N5 N6 N9 N10 N3 N4 N1 N2 N11 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro Devices IO_L26P_2 IO_L27N_2 IO_L27P_2 IO_L28N_2/VREF_2 IO_L28P_2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2 IO_L40P_2 IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 XC2VPX70 (if Different) Pin Number N12 P9 P10 P7 P8 P11 P12 P5 P6 P1 P2 R9 R10 R5 R6 P3 R3 R1 R2 R11 R12 T6 T7 T8 R8 T4 T5 T2 T3 T10 T11 U7 U8 U5 U6 U9 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Virtex-II Pro Devices IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2 IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 XC2VPX70 (if Different) Pin Number U10 U3 U4 U1 U2 T12 U12 V10 V11 V7 V8 U11 V12 V4 V5 V1 V2 W9 W10 W7 W8 W5 W6 W11 W12 W3 W4 W1 W2 Y9 Y10 Y6 Y7 Y3 Y4 Y11 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 2 2 2 2 2 2 2 2 2 Virtex-II Pro Devices IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 XC2VPX70 (if Different) Pin Number Y12 AA9 AA10 AA6 AA7 AA12 AB12 AA3 AA4 No Connects XC2VP70, XC2VPX70 XC2VP100
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3 IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3
AB3 AB4 AB6 AB7 AB9 AB10 AC3 AC4 AC11 AC12 AC6 AC7 AC9 AC10 AD9 AD10 AD1 AD2 AD3 AD4 AD11 AD12 AD5 AD6 AD7 AD8
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro Devices IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L38N_3 IO_L38P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 XC2VPX70 (if Different) Pin Number AE10 AE11 AE1 AE2 AE4 AE5 AF11 AE12 AE7 AE8 AF1 AF2 AG12 AF12 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AG2 AG3 AG10 AG11 AG4 AG5 AG6 AG7 AG8 AH8 AH1 AH2 AH3 AJ3 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro Devices IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L30N_3 IO_L30P_3 IO_L29N_3 IO_L29P_3 IO_L28N_3 IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L26N_3 IO_L26P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 IO_L18N_3 IO_L18P_3 XC2VPX70 (if Different) Pin Number AH11 AH12 AH5 AH6 AH9 AH10 AJ11 AJ12 AJ1 AJ2 AJ5 AJ6 AJ9 AJ10 AJ7 AJ8 AK1 AK2 AK11 AK12 AK3 AK4 AK5 AK6 AK9 AK10 AK7 AK8 AL2 AL3 AL11 AL12 AL4 AL5 AL7 AL8 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro Devices IO_L17N_3 IO_L17P_3 IO_L16N_3 IO_L16P_3 IO_L15N_3/VREF_3 IO_L15P_3 IO_L14N_3 IO_L14P_3 IO_L13N_3 IO_L13P_3 IO_L12N_3 IO_L12P_3 IO_L11N_3 IO_L11P_3 IO_L10N_3 IO_L10P_3 IO_L09N_3/VREF_3 IO_L09P_3 IO_L08N_3 IO_L08P_3 IO_L07N_3 IO_L07P_3 IO_L84N_3 IO_L84P_3 IO_L83N_3 IO_L83P_3 IO_L82N_3 IO_L82P_3 IO_L81N_3/VREF_3 IO_L81P_3 IO_L80N_3 IO_L80P_3 IO_L79N_3 IO_L79P_3 IO_L78N_3 IO_L78P_3 XC2VPX70 (if Different) Pin Number AL9 AL10 AM1 AM2 AM3 AN3 AM8 AM9 AM4 AM5 AM6 AM7 AN9 AM10 AN1 AN2 AN5 AN6 AN7 AN8 AP1 AP2 AP4 AP5 AR7 AP8 AP6 AP7 AR2 AR3 AT5 AR6 AR4 AR5 AT1 AT2 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro Devices IO_L77N_3 IO_L77P_3 IO_L76N_3 IO_L76P_3 IO_L75N_3/VREF_3 IO_L75P_3 IO_L74N_3 IO_L74P_3 IO_L73N_3 IO_L73P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 XC2VPX70 (if Different) Pin Number AT3 AT4 AU1 AU2 AU3 AU4 AV3 AW3 AV1 AV2 AW1 AW2 AT8 AU8 AT6 AU7 AY5 AY6 AV7 AW7 AV6 AW6 No Connects XC2VP70, XC2VPX70 XC2VP100
4 4 4 4 4 4 4 4 4 4 4 4 4
AT9 AR9 AU9 AV9 AY9 AW9 AN11 AR10 AP10 AU10 AT10 AV10 AW10
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Virtex-II Pro Devices IO_L09N_4 IO_L09P_4/VREF_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4 IO_L26P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L28N_4 IO_L28P_4 IO_L29N_4 IO_L29P_4 IO_L30N_4 IO_L30P_4 IO_L34N_4 IO_L34P_4 IO_L35N_4 IO_L35P_4 IO_L36N_4 IO_L36P_4/VREF_4 IO_L78N_4 IO_L78P_4 IO_L83_4/No_Pair IO_L84N_4 IO_L84P_4 IO_L85N_4 IO_L85P_4 IO_L86N_4 IO_L86P_4 IO_L87N_4 XC2VPX70 (if Different) Pin Number AR11 AP11 AV11 AU11 AY10 AY11 AN12 AM12 AR12 AP12 AT12 AU12 AW12 AV12 AM13 AL13 AP13 AN13 AT13 AR13 AV13 AU13 AW13 AY13 AL15 AL14 AN14 AM14 AR14 AU14 AT14 AW14 AV14 AM15 AN15 AR15 NC NC NC NC NC NC NC NC NC NC No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
www.xilinx.com
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Virtex-II Pro Devices IO_L87P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4 IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L58N_4 IO_L58P_4 IO_L59N_4 IO_L59P_4 IO_L60N_4 XC2VPX70 (if Different) Pin Number AP15 AV15 AU15 AY14 AY15 AM16 AL16 AP16 AN16 AR16 AT16 AV16 AU16 AL18 AL17 AM17 AN17 AR17 AP17 AU17 AT17 AW16 AW17 AN18 AM18 AT18 AR18 AV17 AV18 AY18 AY17 AM19 AL19 AP19 AN19 AT19 No Connects XC2VP70, XC2VPX70 NC XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Virtex-II Pro Devices IO_L60P_4 IO_L64N_4 IO_L64P_4 IO_L65N_4 IO_L65P_4 IO_L66N_4 IO_L66P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P XC2VPX70 (if Different) Pin Number AR19 AV19 AU19 AW19 AY19 AL21 AL20 AN20 AM20 AP20 AR20 AV20 AU20 AY20 AW20 AN21 AP21 AU21 AT21 No Connects XC2VP70, XC2VPX70 XC2VP100
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L66N_5/VREF_5 IO_L66P_5 IO_L65N_5 IO_L65P_5
BREFCLKN BREFCLKP
AT22 AU22 AP22 AN22 AW23 AY23 AU23 AV23 AR23 AP23 AM23 AN23 AL23 AL22 AY24 AW24
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Virtex-II Pro Devices IO_L64N_5 IO_L64P_5 IO_L60N_5 IO_L60P_5 IO_L59N_5 IO_L59P_5 IO_L58N_5 IO_L58P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 XC2VPX70 (if Different) Pin Number AU24 AV24 AR24 AT24 AN24 AP24 AL24 AM24 AY26 AY25 AV25 AV26 AR25 AT25 AM25 AN25 AW26 AW27 AT26 AU26 AP26 AR26 AN26 AM26 AL26 AL25 AU27 AV27 AT27 AR27 AN27 AP27 AL27 AM27 AY28 AY29 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Virtex-II Pro Devices IO_L37N_5 IO_L37P_5 IO_L87N_5/VREF_5 IO_L87P_5 IO_L86N_5 IO_L86P_5 IO_L85N_5 IO_L85P_5 IO_L84N_5 IO_L84P_5 IO_L83_5/No_Pair IO_L78N_5 IO_L78P_5 IO_L36N_5/VREF_5 IO_L36P_5 IO_L35N_5 IO_L35P_5 IO_L34N_5 IO_L34P_5 IO_L30N_5 IO_L30P_5 IO_L29N_5 IO_L29P_5 IO_L28N_5 IO_L28P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L21N_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 XC2VPX70 (if Different) Pin Number AU28 AV28 AP28 AR28 AN28 AM28 AV29 AW29 AT29 AU29 AR29 AM29 AN29 AL29 AL28 AY30 AW30 AU30 AV30 AR30 AT30 AN30 AP30 AL30 AM30 AV31 AW31 AU31 AT31 AP31 AR31 AM31 AN31 AY32 AY33 AU32 NC NC NC NC NC NC NC NC NC NC NC No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Virtex-II Pro Devices IO_L19P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B XC2VPX70 (if Different) Pin Number AV32 AP32 AR32 AW33 AV33 AT33 AU33 AP33 AR33 AN32 AW34 AY34 AV34 AU34 AR34 AT34 No Connects XC2VP70, XC2VPX70 XC2VP100
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L73P_6 IO_L73N_6 IO_L74P_6 IO_L74N_6 IO_L75P_6 IO_L75N_6/VREF_6 IO_L76P_6
AW37 AV37 AW36 AV36 AY37 AY38 AU36 AT37 AU35 AT35 AW41 AW42 AV41 AV42 AW40 AV40 AU39 AU40 AU41
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro Devices IO_L76N_6 IO_L77P_6 IO_L77N_6 IO_L78P_6 IO_L78N_6 IO_L79P_6 IO_L79N_6 IO_L80P_6 IO_L80N_6 IO_L81P_6 IO_L81N_6/VREF_6 IO_L82P_6 IO_L82N_6 IO_L83P_6 IO_L83N_6 IO_L84P_6 IO_L84N_6 IO_L07P_6 IO_L07N_6 IO_L08P_6 IO_L08N_6 IO_L09P_6 IO_L09N_6/VREF_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6/VREF_6 IO_L16P_6 XC2VPX70 (if Different) Pin Number AU42 AT39 AT40 AT41 AT42 AR38 AR39 AR37 AT38 AR40 AR41 AP36 AP37 AP35 AR36 AP38 AP39 AP41 AP42 AN35 AN36 AN37 AN38 AN41 AN42 AM33 AN34 AM36 AM37 AM38 AM39 AM34 AM35 AN40 AM40 AM41 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro Devices IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 IO_L25N_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6 IO_L33N_6/VREF_6 IO_L34P_6 XC2VPX70 (if Different) Pin Number AM42 AL33 AL34 AL35 AL36 AL38 AL39 AL31 AL32 AL40 AL41 AK35 AK36 AK33 AK34 AK37 AK38 AK39 AK40 AK31 AK32 AK41 AK42 AJ35 AJ36 AJ33 AJ34 AJ37 AJ38 AJ41 AJ42 AJ31 AJ32 AH33 AH34 AH37 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro Devices IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6 IO_L52P_6 XC2VPX70 (if Different) Pin Number AH38 AH31 AH32 AJ40 AH40 AH41 AH42 AH35 AG35 AG36 AG37 AG38 AG39 AG32 AG33 AG40 AG41 AF33 AF34 AF35 AF36 AF37 AF38 AF39 AF40 AF31 AG31 AF41 AF42 AE35 AE36 AE31 AF32 AE38 AE39 AE41 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Virtex-II Pro Devices IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 XC2VPX70 (if Different) Pin Number AE42 AE32 AE33 AD35 AD36 AD37 AD38 AD31 AD32 AD39 AD40 AD41 AD42 AD33 AD34 AC33 AC34 AC36 AC37 AC31 AC32 AC39 AC40 AB33 AB34 AB36 AB37 AB39 AB40 No Connects XC2VP70, XC2VPX70 XC2VP100
7 7 7 7 7 7
IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7
AA39 AA40 AB31 AA31 AA36 AA37
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro Devices IO_L87P_7 IO_L87N_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 XC2VPX70 (if Different) Pin Number AA33 AA34 Y31 Y32 Y39 Y40 Y36 Y37 Y33 Y34 W41 W42 W39 W40 W31 W32 W37 W38 W35 W36 W33 W34 V41 V42 V38 V39 V31 U32 V35 V36 V32 V33 U31 T31 U41 U42 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro Devices IO_L45P_7 IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L30P_7 IO_L30N_7 IO_L29P_7 IO_L29N_7 IO_L28P_7 IO_L28N_7/VREF_7 XC2VPX70 (if Different) Pin Number U39 U40 U33 U34 U37 U38 U35 U36 T32 T33 T40 T41 T38 T39 R35 T35 T36 T37 R31 R32 R41 R42 R40 P40 R37 R38 R33 R34 P41 P42 P37 P38 P31 P32 P35 P36 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro Devices IO_L27P_7 IO_L27N_7 IO_L26P_7 IO_L26N_7 IO_L25P_7 IO_L25N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7/VREF_7 IO_L21P_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L18P_7 IO_L18N_7 IO_L17P_7 IO_L17N_7 IO_L16P_7 IO_L16N_7/VREF_7 IO_L15P_7 IO_L15N_7 IO_L14P_7 IO_L14N_7 IO_L13P_7 IO_L13N_7 IO_L12P_7 IO_L12N_7 IO_L11P_7 IO_L11N_7 IO_L10P_7 IO_L10N_7/VREF_7 XC2VPX70 (if Different) Pin Number P33 P34 N31 N32 N41 N42 N39 N40 N33 N34 N37 N38 N35 N36 M38 M39 M40 M41 M33 M34 M31 M32 M35 M36 L41 L42 L39 L38 L40 K40 L36 L37 L34 L35 K42 K41 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro Devices IO_L09P_7 IO_L09N_7 IO_L08P_7 IO_L08N_7 IO_L07P_7 IO_L07N_7 IO_L84P_7 IO_L84N_7 IO_L83P_7 IO_L83N_7 IO_L82P_7 IO_L82N_7/VREF_7 IO_L81P_7 IO_L81N_7 IO_L80P_7 IO_L80N_7 IO_L79P_7 IO_L79N_7 IO_L78P_7 IO_L78N_7 IO_L77P_7 IO_L77N_7 IO_L76P_7 IO_L76N_7/VREF_7 IO_L75P_7 IO_L75N_7 IO_L74P_7 IO_L74N_7 IO_L73P_7 IO_L73N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 XC2VPX70 (if Different) Pin Number K36 K35 K38 K37 L33 K34 J41 J42 J39 J38 J36 J37 J35 H36 H41 H40 H38 H39 H37 G38 G42 G41 G39 G40 F41 F42 F40 F39 E41 E42 D41 D42 E40 D40 F36 G37 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 Virtex-II Pro Devices IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 XC2VPX70 (if Different) Pin Number D37 E37 D36 E36 C37 C38 No Connects XC2VP70, XC2VPX70 XC2VP100
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1
D25 G23 G28 G32 J25 J29 P22 P23 P24 P25 P26 R22 R23 R24 R25 R21 R20 R19 R18 P21 P20 P19 P18 P17 J18 J14 G20 G15 G11
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Virtex-II Pro Devices VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 XC2VPX70 (if Different) Pin Number D18 AA15 AA14 Y15 Y14 Y8 Y5 W15 W14 V15 V14 V3 U15 U14 T15 T14 R14 T9 P4 M6 J3 F5 AU5 AP3 AL6 AJ4 AH14 AG15 AG14 AG9 AF15 AF14 AE15 AE14 AE3 AD15 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Virtex-II Pro Devices VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 XC2VPX70 (if Different) Pin Number AD14 AC15 AC14 AC8 AC5 AB15 AB14 AW18 AT20 AT15 AT11 AP18 AP14 AJ21 AJ20 AJ19 AJ18 AJ17 AH21 AH20 AH19 AH18 AW25 AT32 AT28 AT23 AP29 AP25 AJ26 AJ25 AJ24 AJ23 AJ22 AH25 AH24 AH23 No Connects XC2VP70, XC2VPX70 XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Virtex-II Pro Devices VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 XC2VPX70 (if Different) Pin Number AH22 AU38 AP40 AL37 AJ39 AH29 AG34 AG29 AG28 AF29 AF28 AE40 AE29 AE28 AD29 AD28 AC38 AC35 AC29 AC28 AB29 AB28 AA29 AA28 Y38 Y35 Y29 Y28 W29 W28 V40 V29 V28 U29 U28 T34 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank 7 7 7 7 7 7 7 Virtex-II Pro Devices VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 XC2VPX70 (if Different) Pin Number T29 T28 R29 P39 M37 J40 F38 No Connects XC2VP70, XC2VPX70 XC2VP100
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
CCLK PROG_B DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX2 VTTXPAD2 TXNPAD2 TXPPAD2 GNDA2 RXPPAD2 RXNPAD2 VTRXPAD2 AVCCAUXRX2 AVCCAUXTX3 VTTXPAD3 TXNPAD3
AY7 G35 AW8 AV35 AY36 AW35 G8 C36 C7 F8 AV8 F35 D8 E8 E35 D35 B40 B41 A41 A40 C39 A39 A38 B39 B38 B36 B37 A37
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices TXPPAD3 GNDA3 RXPPAD3 RXNPAD3 VTRXPAD3 AVCCAUXRX3 AVCCAUXTX4 VTTXPAD4 TXNPAD4 TXPPAD4 GNDA4 RXPPAD4 RXNPAD4 VTRXPAD4 AVCCAUXRX4 AVCCAUXTX5 VTTXPAD5 TXNPAD5 TXPPAD5 GNDA5 RXPPAD5 RXNPAD5 VTRXPAD5 AVCCAUXRX5 AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 XC2VPX70 (if Different) Pin Number A36 C35 A35 A34 B35 B34 B32 B33 A33 A32 C31 A31 A30 B31 B30 B28 B29 A29 A28 C27 A27 A26 B27 B26 B24 B25 A25 A24 C22 A23 A22 B23 B22 B20 B21 A21 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices TXPPAD7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXTX8 VTTXPAD8 TXNPAD8 TXPPAD8 GNDA8 RXPPAD8 RXNPAD8 VTRXPAD8 AVCCAUXRX8 AVCCAUXTX9 VTTXPAD9 TXNPAD9 TXPPAD9 GNDA9 RXPPAD9 RXNPAD9 VTRXPAD9 AVCCAUXRX9 AVCCAUXTX10 VTTXPAD10 TXNPAD10 TXPPAD10 GNDA10 RXPPAD10 RXNPAD10 VTRXPAD10 AVCCAUXRX10 AVCCAUXTX11 VTTXPAD11 TXNPAD11 XC2VPX70 (if Different) Pin Number A20 C21 A19 A18 B19 B18 B16 B17 A17 A16 C16 A15 A14 B15 B14 B12 B13 A13 A12 C12 A11 A10 B11 B10 B8 B9 A9 A8 C8 A7 A6 B7 B6 B4 B5 A5 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices TXPPAD11 GNDA11 RXPPAD11 RXNPAD11 VTRXPAD11 AVCCAUXRX11 AVCCAUXRX14 VTRXPAD14 RXNPAD14 RXPPAD14 GNDA14 TXPPAD14 TXNPAD14 VTTXPAD14 AVCCAUXTX14 AVCCAUXRX15 VTRXPAD15 RXNPAD15 RXPPAD15 GNDA15 TXPPAD15 TXNPAD15 VTTXPAD15 AVCCAUXTX15 AVCCAUXRX16 VTRXPAD16 RXNPAD16 RXPPAD16 GNDA16 TXPPAD16 TXNPAD16 VTTXPAD16 AVCCAUXTX16 AVCCAUXRX17 VTRXPAD17 RXNPAD17 XC2VPX70 (if Different) Pin Number A4 C4 A3 A2 B3 B2 BA2 BA3 BB2 BB3 AY4 BB4 BB5 BA5 BA4 BA6 BA7 BB6 BB7 AY8 BB8 BB9 BA9 BA8 BA10 BA11 BB10 BB11 AY12 BB12 BB13 BA13 BA12 BA14 BA15 BB14 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices RXPPAD17 GNDA17 TXPPAD17 TXNPAD17 VTTXPAD17 AVCCAUXTX17 AVCCAUXRX18 VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 AVCCAUXRX20 VTRXPAD20 RXNPAD20 RXPPAD20 GNDA20 TXPPAD20 TXNPAD20 VTTXPAD20 AVCCAUXTX20 AVCCAUXRX21 VTRXPAD21 RXNPAD21 XC2VPX70 (if Different) Pin Number BB15 AY16 BB16 BB17 BA17 BA16 BA18 BA19 BB18 BB19 AY21 BB20 BB21 BA21 BA20 BA22 BA23 BB22 BB23 AY22 BB24 BB25 BA25 BA24 BA26 BA27 BB26 BB27 AY27 BB28 BB29 BA29 BA28 BA30 BA31 BB30 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices RXPPAD21 GNDA21 TXPPAD21 TXNPAD21 VTTXPAD21 AVCCAUXTX21 AVCCAUXRX22 VTRXPAD22 RXNPAD22 RXPPAD22 GNDA22 TXPPAD22 TXNPAD22 VTTXPAD22 AVCCAUXTX22 AVCCAUXRX23 VTRXPAD23 RXNPAD23 RXPPAD23 GNDA23 TXPPAD23 TXNPAD23 VTTXPAD23 AVCCAUXTX23 XC2VPX70 (if Different) Pin Number BB31 AY31 BB32 BB33 BA33 BA32 BA34 BA35 BB34 BB35 AY35 BB36 BB37 BA37 BA36 BA38 BA39 BB38 BB39 AY39 BB40 BB41 BA41 BA40 No Connects XC2VP70, XC2VPX70 XC2VP100
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
AB27 AB16 AC27 AC16 AD27 AD16 AE27 AE16 AF27 AF26 AF17
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC2VPX70 (if Different) Pin Number AF16 AG27 AG26 AG25 AG24 AG23 AG22 AG21 AG20 AG19 AG18 AG17 AG16 AH28 AH27 AH26 AH17 AH16 AH15 AJ29 AJ28 AJ27 AJ16 AJ15 AJ14 AK30 AK13 AA27 AA16 Y27 Y16 W27 W16 V27 V16 U27 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX XC2VPX70 (if Different) Pin Number U26 U17 U16 T27 T26 T25 T24 T23 T22 T21 T20 T19 T18 T17 T16 R28 R27 R26 R17 R16 R15 P29 P28 P27 P16 P15 P14 N30 N13 AB42 AB41 AB2 AB1 AC42 AC1 AM32 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number AM11 AN33 AN10 AV39 AV4 AW38 AW22 AW21 AW5 AA42 AA41 AA2 AA1 Y42 Y1 L32 L11 K33 K10 E39 E4 D38 D22 D21 D5 AB38 AB35 AB32 AB26 AB25 AB24 AB23 AB22 AB21 AB20 AB19 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number AB18 AB17 AB11 AB8 AB5 AC41 AC26 AC25 AC24 AC23 AC22 AC21 AC20 AC19 AC18 AC17 AC2 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AE37 AE34 AE26 AE25 AE24 AE23 AE22 AE21 AE20 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number AE19 AE18 AE17 AE9 AE6 AF25 AF24 AF23 AF22 AF21 AF20 AF19 AF18 AG42 AG1 AH39 AH36 AH7 AH4 AL42 AL1 AM22 AM21 AN39 AN4 AP34 AP9 AR42 AR35 AR22 AR21 AR8 AR1 AT36 AT7 AU37 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number AU25 AU18 AU6 AV38 AV22 AV21 AV5 AW39 AW32 AW28 AW15 AW11 AW4 AY42 AY41 AY40 AY3 AY2 AY1 BA42 BA1 AA38 AA35 AA32 AA26 AA25 AA24 AA23 AA22 AA21 AA20 AA19 AA18 AA17 AA11 AA8 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number AA5 Y41 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y2 W26 W25 W24 W23 W22 W21 W20 W19 W18 W17 V37 V34 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V9 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number V6 U25 U24 U23 U22 U21 U20 U19 U18 T42 T1 R39 R36 R7 R4 M42 M1 L22 L21 K39 K4 J34 J9 H42 H35 H22 H21 H8 H1 G36 G7 F37 F25 F18 F6 E38 No Connects XC2VP70, XC2VPX70 XC2VP100
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Table 13: FF1704 -- XC2VP70, XC2VPX70, and XC2VP100 Pin Description Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Virtex-II Pro Devices GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC2VPX70 (if Different) Pin Number E22 E21 E5 D39 D32 D28 D15 D11 D4 C42 C41 C40 C3 C2 C1 B42 B1 N14 N29 AK14 AK29 P13 P30 AJ13 AJ30 No Connects XC2VP70, XC2VPX70 XC2VP100
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FF1704 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 9: FF1704 Flip-Chip Fine-Pitch BGA Package Specifications
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FF1696 Flip-Chip Fine-Pitch BGA Package
As shown in Table 14, XC2VP100 Virtex-II Pro devices are available in the FF1696 flip-chip fine-pitch BGA package. Following this table are the FF1696 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 14: FF1696 -- XC2VP100 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DS083 (v4.7) November 5, 2007 Product Specification
Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L05_0/No_Pair IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L19N_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 IO_L21P_0 IO_L25N_0 IO_L25P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0/VREF_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L34N_0
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Pin Number E33 F33 K32 L32 C32 C33 G33 A33 B33 F32 G32 H32 J32 D32 E32 A32 B32 K31 L31 H30 G31 E31 F31 H31 J31 D30 D31 B31 C31 K30 L30 F30 G30 B30
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L34P_0 IO_L35N_0 IO_L35P_0 IO_L36N_0 IO_L36P_0/VREF_0 IO_L76N_0 IO_L76P_0 IO_L77N_0 IO_L77P_0 IO_L78N_0 IO_L78P_0 IO_L79N_0 IO_L79P_0 IO_L80_0/No_Pair IO_L83_0/No_Pair IO_L84N_0 IO_L84P_0 IO_L85N_0 IO_L85P_0 IO_L86N_0 IO_L86P_0 IO_L87N_0 IO_L87P_0/VREF_0 IO_L37N_0 IO_L37P_0 IO_L38N_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L43N_0 IO_L43P_0 IO_L44N_0 IO_L44P_0 IO_L45N_0 IO_L45P_0/VREF_0 IO_L10N_0 IO_L10P_0
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Pin Number C30 L29 M29 H28 G29 E29 F29 J29 K29 D28 C29 A29 B29 L28 M28 G27 G28 E28 F28 J28 K28 C27 C28 A28 B28 L27 M27 H26 H27 E27 F27 J27 K27 D26 D27 A27 B27
XC2VP100
NC NC
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Table 14: FF1696 -- XC2VP100 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L11N_0 IO_L11P_0 IO_L12N_0 IO_L12P_0 IO_L18N_0 IO_L18P_0/VREF_0 IO_L46N_0 IO_L46P_0 IO_L47N_0 IO_L47P_0 IO_L48N_0 IO_L48P_0 IO_L49N_0 IO_L49P_0 IO_L50_0/No_Pair IO_L53_0/No_Pair IO_L54N_0 IO_L54P_0 IO_L55N_0 IO_L55P_0 IO_L56N_0 IO_L56P_0 IO_L57N_0 IO_L57P_0/VREF_0 IO_L58N_0 IO_L58P_0 IO_L59N_0 IO_L59P_0 IO_L60N_0 IO_L60P_0 IO_L64N_0 IO_L64P_0 IO_L65N_0 IO_L65P_0 IO_L66N_0 IO_L66P_0/VREF_0 IO_L67N_0
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Pin Number M25 M26 F26 G26 B26 C26 G24 G25 K26 L26 E25 F25 C24 C25 L24 L25 A25 B25 H23 H24 J25 K25 E24 F24 D23 D24 J24 K24 A24 B24 F23 G23 M22 M23 B23 C23 H22
XC2VP100 NC NC NC NC NC NC
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 255
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L67P_0 IO_L68N_0 IO_L68P_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L73N_0 IO_L73P_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number J22 K23 L23 F22 G22 D22 E22 K22 L22 B22 C22 XC2VP100
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L73N_1 IO_L73P_1 IO_L69N_1/VREF_1 IO_L69P_1 IO_L68N_1 IO_L68P_1 IO_L67N_1 IO_L67P_1 IO_L66N_1/VREF_1 IO_L66P_1 IO_L65N_1 IO_L65P_1 IO_L64N_1 IO_L64P_1 IO_L60N_1 IO_L60P_1 IO_L59N_1 IO_L59P_1 IO_L58N_1 IO_L58P_1 IO_L57N_1/VREF_1
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C21 B21 L21 K21 E21 D21 G21 F21 L20 K20 J21 H21 C20 B20 M20 M21 G20 F20 B19 A19 K19 J19 D19 D20 F19
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 256
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L57P_1 IO_L56N_1 IO_L56P_1 IO_L55N_1 IO_L55P_1 IO_L54N_1 IO_L54P_1 IO_L53_1/No_Pair IO_L50_1/No_Pair IO_L49N_1 IO_L49P_1 IO_L48N_1 IO_L48P_1 IO_L47N_1 IO_L47P_1 IO_L46N_1 IO_L46P_1 IO_L18N_1/VREF_1 IO_L18P_1 IO_L12N_1 IO_L12P_1 IO_L11N_1 IO_L11P_1 IO_L10N_1 IO_L10P_1 IO_L45N_1/VREF_1 IO_L45P_1 IO_L44N_1 IO_L44P_1 IO_L43N_1 IO_L43P_1 IO_L39N_1 IO_L39P_1 IO_L38N_1 IO_L38P_1 IO_L37N_1 IO_L37P_1
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Pin Number E19 K18 J18 H19 H20 B18 A18 L18 L19 C18 C19 F18 E18 L17 K17 G18 G19 C17 B17 G17 F17 M17 M18 B16 A16 D16 D17 K16 J16 F16 E16 H16 H17 M16 L16 B15 A15
XC2VP100
NC NC NC NC NC NC NC NC
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 257
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L87N_1/VREF_1 IO_L87P_1 IO_L86N_1 IO_L86P_1 IO_L85N_1 IO_L85P_1 IO_L84N_1 IO_L84P_1 IO_L83_1/No_Pair IO_L80_1/No_Pair IO_L79N_1 IO_L79P_1 IO_L78N_1 IO_L78P_1 IO_L77N_1 IO_L77P_1 IO_L76N_1 IO_L76P_1 IO_L36N_1/VREF_1 IO_L36P_1 IO_L35N_1 IO_L35P_1 IO_L34N_1 IO_L34P_1 IO_L30N_1 IO_L30P_1 IO_L29N_1 IO_L29P_1 IO_L28N_1 IO_L28P_1 IO_L27N_1/VREF_1 IO_L27P_1 IO_L26N_1 IO_L26P_1 IO_L25N_1 IO_L25P_1 IO_L21N_1
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Pin Number C15 C16 K15 J15 F15 E15 G15 G16 M15 L15 B14 A14 C14 D15 K14 J14 F14 E14 G14 H15 M14 L14 C13 B13 G13 F13 L13 K13 C12 B12 D12 D13 J12 H12 F12 E12 G12
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 258
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Description IO_L21P_1 IO_L20N_1 IO_L20P_1 IO_L19N_1 IO_L19P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L08N_1 IO_L08P_1 IO_L07N_1 IO_L07P_1 IO_L06N_1 IO_L06P_1 IO_L05_1/No_Pair IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 Pin Number H13 L12 K12 B11 A11 E11 D11 J11 H11 G11 F11 B10 A10 G10 C10 C11 L11 K11 F10 E10 XC2VP100
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L73N_2 IO_L73P_2 IO_L74N_2 IO_L74P_2
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B8 A8 C9 B9 B7 A7 B6 A6 D8 D9 B4 A4 C7 C8 G9 F9
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 259
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L75N_2 IO_L75P_2 IO_L76N_2/VREF_2 IO_L76P_2 IO_L77N_2 IO_L77P_2 IO_L78N_2 IO_L78P_2 IO_L79N_2 IO_L79P_2 IO_L80N_2 IO_L80P_2 IO_L81N_2 IO_L81P_2 IO_L82N_2/VREF_2 IO_L82P_2 IO_L83N_2 IO_L83P_2 IO_L84N_2 IO_L84P_2 IO_L61N_2 IO_L61P_2 IO_L62N_2 IO_L62P_2 IO_L63N_2 IO_L63P_2 IO_L64N_2/VREF_2 IO_L64P_2 IO_L65N_2 IO_L65P_2 IO_L66N_2 IO_L66P_2 IO_L67N_2 IO_L67P_2 IO_L68N_2 IO_L68P_2 IO_L69N_2
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Pin Number C5 B5 D7 C6 H8 H9 C3 C4 D1 D2 J8 K9 E6 D5 E4 D4 L8 L9 E3 D3 F8 E8 M8 M9 F7 E7 F3 E2 N12 P12 F1 F2 G7 G8 N10 N11 G6
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 260
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L69P_2 IO_L70N_2/VREF_2 IO_L70P_2 IO_L71N_2 IO_L71P_2 IO_L72N_2 IO_L72P_2 IO_L07N_2 IO_L07P_2 IO_L08N_2 IO_L08P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2/VREF_2 IO_L10P_2 IO_L11N_2 IO_L11P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2 IO_L13P_2 IO_L14N_2 IO_L14P_2 IO_L15N_2 IO_L15P_2 IO_L16N_2/VREF_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L18N_2 IO_L18P_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2
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Pin Number F6 G5 F5 P10 P11 G3 G4 G1 G2 N8 P9 H6 H7 H4 H5 R12 T12 H2 H3 J6 J7 R10 R11 J3 J4 J2 H1 R8 R9 K5 K6 K1 K2 T10 T11 L7 K7
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 261
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L22N_2/VREF_2 IO_L22P_2 IO_L23N_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L26N_2 IO_L26P_2 IO_L27N_2 IO_L27P_2 IO_L28N_2/VREF_2 IO_L28P_2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 IO_L31N_2 IO_L31P_2 IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L34N_2/VREF_2 IO_L34P_2 IO_L35N_2 IO_L35P_2 IO_L36N_2 IO_L36P_2 IO_L37N_2 IO_L37P_2 IO_L38N_2 IO_L38P_2 IO_L39N_2 IO_L39P_2 IO_L40N_2/VREF_2
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Pin Number L4 L5 T8 T9 L3 K3 L1 L2 U12 V12 M7 L6 M5 M6 U10 U11 M3 M4 N6 N7 U7 U8 N3 N4 N2 M2 V10 V11 P6 P7 P1 P2 V8 V9 R6 P5 R4
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 262
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L40P_2 IO_L41N_2 IO_L41P_2 IO_L42N_2 IO_L42P_2 IO_L43N_2 IO_L43P_2 IO_L44N_2 IO_L44P_2 IO_L45N_2 IO_L45P_2 IO_L46N_2/VREF_2 IO_L46P_2 IO_L47N_2 IO_L47P_2 IO_L48N_2 IO_L48P_2 IO_L49N_2 IO_L49P_2 IO_L50N_2 IO_L50P_2 IO_L51N_2 IO_L51P_2 IO_L52N_2/VREF_2 IO_L52P_2 IO_L53N_2 IO_L53P_2 IO_L54N_2 IO_L54P_2 IO_L55N_2 IO_L55P_2 IO_L56N_2 IO_L56P_2 IO_L57N_2 IO_L57P_2 IO_L58N_2/VREF_2 IO_L58P_2
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Pin Number R5 V6 V7 R3 P3 R1 R2 W10 W11 T7 R7 T4 T5 W9 Y10 T1 T2 U6 T6 W7 Y8 U4 T3 U2 U3 Y11 Y12 V4 V5 V1 V2 Y6 Y7 W5 W6 W3 V3
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 263
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description IO_L59N_2 IO_L59P_2 IO_L60N_2 IO_L60P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L87N_2 IO_L87P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L89N_2 IO_L89P_2 IO_L90N_2 IO_L90P_2 Pin Number AA11 AA12 W1 W2 Y2 Y3 AA9 AA10 AA5 AA6 AA4 Y4 AA7 AA8 AA2 AA3 XC2VP100
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L88N_3 IO_L88P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L86N_3 IO_L86P_3 IO_L85N_3 IO_L85P_3 IO_L60N_3 IO_L60P_3 IO_L59N_3 IO_L59P_3 IO_L58N_3 IO_L58P_3 IO_L57N_3/VREF_3 IO_L57P_3
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AB5 AB6 AB11 AB12 AB2 AB3 AB4 AC4 AB9 AB10 AC2 AC3 AD5 AD6 AB7 AB8 AD1 AD2 AE4 AE5
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 264
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L56N_3 IO_L56P_3 IO_L55N_3 IO_L55P_3 IO_L54N_3 IO_L54P_3 IO_L53N_3 IO_L53P_3 IO_L52N_3 IO_L52P_3 IO_L51N_3/VREF_3 IO_L51P_3 IO_L50N_3 IO_L50P_3 IO_L49N_3 IO_L49P_3 IO_L48N_3 IO_L48P_3 IO_L47N_3 IO_L47P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3 IO_L44N_3 IO_L44P_3 IO_L43N_3 IO_L43P_3 IO_L42N_3 IO_L42P_3 IO_L41N_3 IO_L41P_3 IO_L40N_3 IO_L40P_3 IO_L39N_3/VREF_3 IO_L39P_3 IO_L38N_3
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Pin Number AC11 AC12 AD3 AE3 AE1 AE2 AC6 AC7 AF2 AF3 AF6 AG6 AD10 AD11 AG4 AG5 AF4 AG3 AC10 AD9 AG1 AG2 AG7 AH7 AC8 AD7 AH4 AH5 AH1 AH2 AE10 AE11 AJ6 AJ7 AH6 AJ5 AE8
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 265
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L38P_3 IO_L37N_3 IO_L37P_3 IO_L36N_3 IO_L36P_3 IO_L35N_3 IO_L35P_3 IO_L34N_3 IO_L34P_3 IO_L33N_3/VREF_3 IO_L33P_3 IO_L32N_3 IO_L32P_3 IO_L31N_3 IO_L31P_3 IO_L30N_3 IO_L30P_3 IO_L29N_3 IO_L29P_3 IO_L28N_3 IO_L28P_3 IO_L27N_3/VREF_3 IO_L27P_3 IO_L26N_3 IO_L26P_3 IO_L25N_3 IO_L25P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3 IO_L22N_3 IO_L22P_3 IO_L21N_3/VREF_3 IO_L21P_3 IO_L20N_3 IO_L20P_3
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Pin Number AE9 AH3 AJ3 AJ1 AJ2 AE6 AE7 AK6 AK7 AK3 AK4 AE12 AF12 AL5 AL6 AL3 AL4 AF10 AF11 AK2 AL2 AL7 AM6 AF7 AF8 AM4 AM5 AM1 AM2 AG10 AG11 AM7 AN7 AN5 AN6 AG8 AG9
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 266
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L19N_3 IO_L19P_3 IO_L18N_3 IO_L18P_3 IO_L17N_3 IO_L17P_3 IO_L16N_3 IO_L16P_3 IO_L15N_3/VREF_3 IO_L15P_3 IO_L14N_3 IO_L14P_3 IO_L13N_3 IO_L13P_3 IO_L12N_3 IO_L12P_3 IO_L11N_3 IO_L11P_3 IO_L10N_3 IO_L10P_3 IO_L09N_3/VREF_3 IO_L09P_3 IO_L08N_3 IO_L08P_3 IO_L07N_3 IO_L07P_3 IO_L72N_3 IO_L72P_3 IO_L71N_3 IO_L71P_3 IO_L70N_3 IO_L70P_3 IO_L69N_3/VREF_3 IO_L69P_3 IO_L68N_3 IO_L68P_3 IO_L67N_3
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Pin Number AM3 AN3 AN1 AN2 AG12 AH12 AP6 AP7 AP3 AP4 AH10 AH11 AR6 AR7 AR4 AR5 AH8 AH9 AR2 AR3 AP2 AR1 AJ10 AJ11 AT7 AT8 AT3 AT4 AJ12 AK12 AT1 AT2 AT6 AU6 AK10 AK11 AT5
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 267
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L67P_3 IO_L66N_3 IO_L66P_3 IO_L65N_3 IO_L65P_3 IO_L64N_3 IO_L64P_3 IO_L63N_3/VREF_3 IO_L63P_3 IO_L62N_3 IO_L62P_3 IO_L61N_3 IO_L61P_3 IO_L84N_3 IO_L84P_3 IO_L83N_3 IO_L83P_3 IO_L82N_3 IO_L82P_3 IO_L81N_3/VREF_3 IO_L81P_3 IO_L80N_3 IO_L80P_3 IO_L79N_3 IO_L79P_3 IO_L78N_3 IO_L78P_3 IO_L77N_3 IO_L77P_3 IO_L76N_3 IO_L76P_3 IO_L75N_3/VREF_3 IO_L75P_3 IO_L74N_3 IO_L74P_3 IO_L73N_3 IO_L73P_3
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Pin Number AU5 AU1 AU2 AJ9 AK8 AU8 AV8 AU7 AV7 AL8 AL9 AU3 AV2 AV6 AW5 AM8 AM9 AV4 AW4 AV3 AW3 AN9 AP8 AW1 AW2 AY7 AY8 AR8 AR9 AW7 AY6 AY3 AY4 AT9 AU9 AY5 BA5
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 268
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 Pin Description IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3 IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/BUSY/DOUT (1) IO_L01P_4/INIT_B IO_L02N_4/D0/DIN (1) IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L05_4/No_Pair IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07N_4 IO_L07P_4/VREF_4 IO_L08N_4 IO_L08P_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L19N_4 IO_L19P_4 IO_L20N_4 IO_L20P_4 IO_L21N_4 IO_L21P_4 IO_L25N_4 IO_L25P_4 IO_L26N_4
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Pin Number BA8 BB8 AW8 AW9 BA7 BB7 BA6 BB6 AY9 BA9 BA4 BB4
XC2VP100
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
AL11 AL12 AV10 AU10 AN11 AM11 AT10 AY11 AY10 BB10 BA10 AU11 AT11 AR11 AP11 AW11 AV11 BB11 BA11 AN12 AM12 AR13 AT12 AV12
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 269
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L26P_4 IO_L27N_4 IO_L27P_4/VREF_4 IO_L28N_4 IO_L28P_4 IO_L29N_4 IO_L29P_4 IO_L30N_4 IO_L30P_4 IO_L34N_4 IO_L34P_4 IO_L35N_4 IO_L35P_4 IO_L36N_4 IO_L36P_4/VREF_4 IO_L76N_4 IO_L76P_4 IO_L77N_4 IO_L77P_4 IO_L78N_4 IO_L78P_4 IO_L79N_4 IO_L79P_4 IO_L80_4/No_Pair IO_L83_4/No_Pair IO_L84N_4 IO_L84P_4 IO_L85N_4 IO_L85P_4 IO_L86N_4 IO_L86P_4 IO_L87N_4 IO_L87P_4/VREF_4 IO_L37N_4 IO_L37P_4 IO_L38N_4 IO_L38P_4
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Pin Number AU12 AR12 AP12 AW13 AW12 BA12 AY12 AN13 AM13 AU13 AT13 BA13 AY13 AM14 AL14 AR15 AT14 AV14 AU14 AP14 AN14 AW15 AY14 BB14 BA14 AM15 AL15 AT16 AT15 AV15 AU15 AP15 AN15 AY16 AY15 BB15 BA15
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 270
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L39N_4 IO_L39P_4 IO_L43N_4 IO_L43P_4 IO_L44N_4 IO_L44P_4 IO_L45N_4 IO_L45P_4/VREF_4 IO_L10N_4 IO_L10P_4 IO_L11N_4 IO_L11P_4 IO_L12N_4 IO_L12P_4 IO_L16N_4 IO_L16P_4 IO_L18N_4 IO_L18P_4/VREF_4 IO_L46N_4 IO_L46P_4 IO_L47N_4 IO_L47P_4 IO_L48N_4 IO_L48P_4 IO_L49N_4 IO_L49P_4 IO_L50_4/No_Pair IO_L53_4/No_Pair IO_L54N_4 IO_L54P_4 IO_L55N_4 IO_L55P_4 IO_L56N_4 IO_L56P_4 IO_L57N_4 IO_L57P_4/VREF_4 IO_L58N_4
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Pin Number AM16 AL16 AR17 AR16 AV16 AU16 AP16 AN16 AW17 AW16 BB16 BA16 AL18 AL17 AU17 AT17 BA17 AY17 AT19 AT18 AN17 AM17 AV18 AU18 AY19 AY18 AM19 AM18 BB18 BA18 AR20 AR19 AP18 AN18 AV19 AU19 AW20
XC2VP100
NC NC NC NC NC NC NC NC NC NC
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 271
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L58P_4 IO_L59N_4 IO_L59P_4 IO_L60N_4 IO_L60P_4 IO_L64N_4 IO_L64P_4 IO_L65N_4 IO_L65P_4 IO_L66N_4 IO_L66P_4/VREF_4 IO_L67N_4 IO_L67P_4 IO_L68N_4 IO_L68P_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L73N_4 IO_L73P_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P Pin Number AW19 AP19 AN19 BB19 BA19 AU20 AT20 AL21 AL20 BA20 AY20 AR21 AP21 AN20 AM20 AU21 AT21 AW21 AV21 AN21 AM21 BA21 AY21 XC2VP100
5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L73N_5 IO_L73P_5 IO_L69N_5/VREF_5 IO_L69P_5 IO_L68N_5 IO_L68P_5 IO_L67N_5 IO_L67P_5 IO_L66N_5/VREF_5
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AY22 BA22 AM22 AN22 AV22 AW22 AT22 AU22 AM23 AN23 AP22 AR22 AY23
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L66P_5 IO_L65N_5 IO_L65P_5 IO_L64N_5 IO_L64P_5 IO_L60N_5 IO_L60P_5 IO_L59N_5 IO_L59P_5 IO_L58N_5 IO_L58P_5 IO_L57N_5/VREF_5 IO_L57P_5 IO_L56N_5 IO_L56P_5 IO_L55N_5 IO_L55P_5 IO_L54N_5 IO_L54P_5 IO_L53_5/No_Pair IO_L50_5/No_Pair IO_L49N_5 IO_L49P_5 IO_L48N_5 IO_L48P_5 IO_L47N_5 IO_L47P_5 IO_L46N_5 IO_L46P_5 IO_L18N_5/VREF_5 IO_L18P_5 IO_L16N_5 IO_L16P_5 IO_L12N_5 IO_L12P_5 IO_L11N_5 IO_L11P_5
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Pin Number BA23 AL23 AL22 AT23 AU23 BA24 BB24 AN24 AP24 AW24 AW23 AU24 AV24 AN25 AP25 AR24 AR23 BA25 BB25 AM25 AM24 AY25 AY24 AU25 AV25 AM26 AN26 AT25 AT24 AY26 BA26 AT26 AU26 AL26 AL25 BA27 BB27
XC2VP100
NC NC NC NC NC NC NC NC
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L10N_5 IO_L10P_5 IO_L45N_5/VREF_5 IO_L45P_5 IO_L44N_5 IO_L44P_5 IO_L43N_5 IO_L43P_5 IO_L39N_5 IO_L39P_5 IO_L38N_5 IO_L38P_5 IO_L37N_5 IO_L37P_5 IO_L87N_5/VREF_5 IO_L87P_5 IO_L86N_5 IO_L86P_5 IO_L85N_5 IO_L85P_5 IO_L84N_5 IO_L84P_5 IO_L83_5/No_Pair IO_L80_5/No_Pair IO_L79N_5 IO_L79P_5 IO_L78N_5 IO_L78P_5 IO_L77N_5 IO_L77P_5 IO_L76N_5 IO_L76P_5 IO_L36N_5/VREF_5 IO_L36P_5 IO_L35N_5 IO_L35P_5 IO_L34N_5
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Pin Number AW27 AW26 AN27 AP27 AU27 AV27 AR27 AR26 AL27 AM27 BA28 BB28 AY28 AY27 AN28 AP28 AU28 AV28 AT28 AT27 AL28 AM28 BA29 BB29 AY29 AW28 AN29 AP29 AU29 AV29 AT29 AR28 AL29 AM29 AY30 BA30 AT30
XC2VP100 NC NC
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Description IO_L34P_5 IO_L30N_5 IO_L30P_5 IO_L29N_5 IO_L29P_5 IO_L28N_5 IO_L28P_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L26N_5 IO_L26P_5 IO_L25N_5 IO_L25P_5 IO_L21N_5 IO_L21P_5 IO_L20N_5 IO_L20P_5 IO_L19N_5 IO_L19P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L08N_5 IO_L08P_5 IO_L07N_5/VREF_5 IO_L07P_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L05_5/No_Pair IO_L03N_5/D4 IO_L03P_5/D5 IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B Pin Number AU30 AM30 AN30 AY31 BA31 AW31 AW30 AP31 AR31 AU31 AV31 AT31 AR30 AM31 AN31 BA32 BB32 AV32 AW32 AP32 AR32 AT32 AU32 BA33 BB33 AY33 AY32 AT33 AM32 AN32 AU33 AV33 AL31 AL32 XC2VP100
6 6
IO_L01P_6/VRN_6 IO_L01N_6/VRP_6
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BB39 BA39
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L73P_6 IO_L73N_6 IO_L74P_6 IO_L74N_6 IO_L75P_6 IO_L75N_6/VREF_6 IO_L76P_6 IO_L76N_6 IO_L77P_6 IO_L77N_6 IO_L78P_6 IO_L78N_6 IO_L79P_6 IO_L79N_6 IO_L80P_6 IO_L80N_6 IO_L81P_6 IO_L81N_6/VREF_6 IO_L82P_6 IO_L82N_6 IO_L83P_6 IO_L83N_6 IO_L84P_6 IO_L84N_6 IO_L61P_6 IO_L61N_6 IO_L62P_6
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Pin Number BA34 AY34 BB37 BA37 BB36 BA36 AW34 AW35 BB35 BA35 BA38 AY38 AU34 AT34 AY39 AY40 AY37 AW36 AR34 AR35 AY35 AY36 AW41 AW42 AP35 AN34 AW40 AV40 AW39 AV39 AM34 AM35 AW38 AV37 AV41 AU40 AL34
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L62N_6 IO_L63P_6 IO_L63N_6/VREF_6 IO_L64P_6 IO_L64N_6 IO_L65P_6 IO_L65N_6 IO_L66P_6 IO_L66N_6 IO_L67P_6 IO_L67N_6 IO_L68P_6 IO_L68N_6 IO_L69P_6 IO_L69N_6/VREF_6 IO_L70P_6 IO_L70N_6 IO_L71P_6 IO_L71N_6 IO_L72P_6 IO_L72N_6 IO_L07P_6 IO_L07N_6 IO_L08P_6 IO_L08N_6 IO_L09P_6 IO_L09N_6/VREF_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6
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Pin Number AL35 AV36 AU36 AV35 AU35 AK35 AJ34 AU41 AU42 AU38 AT38 AK32 AK33 AU37 AT37 AT41 AT42 AK31 AJ31 AT39 AT40 AT35 AT36 AJ32 AJ33 AR42 AP41 AR40 AR41 AH34 AH35 AR38 AR39 AR36 AR37 AH32 AH33
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L15P_6 IO_L15N_6/VREF_6 IO_L16P_6 IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_6 IO_L21P_6 IO_L21N_6/VREF_6 IO_L22P_6 IO_L22N_6 IO_L23P_6 IO_L23N_6 IO_L24P_6 IO_L24N_6 IO_L25P_6 IO_L25N_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6/VREF_6 IO_L28P_6 IO_L28N_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 IO_L33P_6
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Pin Number AP39 AP40 AP36 AP37 AH31 AG31 AN41 AN42 AN40 AM40 AG34 AG35 AN37 AN38 AN36 AM36 AG32 AG33 AM41 AM42 AM38 AM39 AF35 AF36 AM37 AL36 AL41 AK41 AF32 AF33 AL39 AL40 AL37 AL38 AF31 AE31 AK39
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 278
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L33N_6/VREF_6 IO_L34P_6 IO_L34N_6 IO_L35P_6 IO_L35N_6 IO_L36P_6 IO_L36N_6 IO_L37P_6 IO_L37N_6 IO_L38P_6 IO_L38N_6 IO_L39P_6 IO_L39N_6/VREF_6 IO_L40P_6 IO_L40N_6 IO_L41P_6 IO_L41N_6 IO_L42P_6 IO_L42N_6 IO_L43P_6 IO_L43N_6 IO_L44P_6 IO_L44N_6 IO_L45P_6 IO_L45N_6/VREF_6 IO_L46P_6 IO_L46N_6 IO_L47P_6 IO_L47N_6 IO_L48P_6 IO_L48N_6 IO_L49P_6 IO_L49N_6 IO_L50P_6 IO_L50N_6 IO_L51P_6 IO_L51N_6/VREF_6
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Pin Number AK40 AK36 AK37 AE36 AE37 AJ41 AJ42 AJ40 AH40 AE34 AE35 AJ38 AH37 AJ36 AJ37 AE32 AE33 AH41 AH42 AH38 AH39 AD36 AC35 AH36 AG36 AG41 AG42 AD34 AC33 AG40 AF39 AG38 AG39 AD32 AD33 AG37 AF37
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 279
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Description IO_L52P_6 IO_L52N_6 IO_L53P_6 IO_L53N_6 IO_L54P_6 IO_L54N_6 IO_L55P_6 IO_L55N_6 IO_L56P_6 IO_L56N_6 IO_L57P_6 IO_L57N_6/VREF_6 IO_L58P_6 IO_L58N_6 IO_L59P_6 IO_L59N_6 IO_L60P_6 IO_L60N_6 IO_L85P_6 IO_L85N_6 IO_L86P_6 IO_L86N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L88P_6 IO_L88N_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 Pin Number AF40 AF41 AC36 AC37 AE41 AE42 AE40 AD40 AC31 AC32 AE38 AE39 AD41 AD42 AB35 AB36 AD37 AD38 AC40 AC41 AB33 AB34 AC39 AB39 AB40 AB41 AB31 AB32 AB37 AB38 XC2VP100
7 7 7 7 7 7
IO_L90P_7 IO_L90N_7 IO_L89P_7 IO_L89N_7 IO_L88P_7 IO_L88N_7/VREF_7
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AA40 AA41 AA35 AA36 Y39 AA39
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 280
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L87P_7 IO_L87N_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L60P_7 IO_L60N_7 IO_L59P_7 IO_L59N_7 IO_L58P_7 IO_L58N_7/VREF_7 IO_L57P_7 IO_L57N_7 IO_L56P_7 IO_L56N_7 IO_L55P_7 IO_L55N_7 IO_L54P_7 IO_L54N_7 IO_L53P_7 IO_L53N_7 IO_L52P_7 IO_L52N_7/VREF_7 IO_L51P_7 IO_L51N_7 IO_L50P_7 IO_L50N_7 IO_L49P_7 IO_L49N_7 IO_L48P_7 IO_L48N_7 IO_L47P_7 IO_L47N_7 IO_L46P_7 IO_L46N_7/VREF_7 IO_L45P_7
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Pin Number AA37 AA38 AA33 AA34 Y40 Y41 W41 W42 AA31 AA32 V40 W40 W37 W38 Y36 Y37 V41 V42 V38 V39 Y31 Y32 U40 U41 T40 U39 Y35 W36 T37 U37 T41 T42 Y33 W34 T38 T39 R36
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 281
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L45N_7 IO_L44P_7 IO_L44N_7 IO_L43P_7 IO_L43N_7 IO_L42P_7 IO_L42N_7 IO_L41P_7 IO_L41N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L39P_7 IO_L39N_7 IO_L38P_7 IO_L38N_7 IO_L37P_7 IO_L37N_7 IO_L36P_7 IO_L36N_7 IO_L35P_7 IO_L35N_7 IO_L34P_7 IO_L34N_7/VREF_7 IO_L33P_7 IO_L33N_7 IO_L32P_7 IO_L32N_7 IO_L31P_7 IO_L31N_7 IO_L30P_7 IO_L30N_7 IO_L29P_7 IO_L29N_7 IO_L28P_7 IO_L28N_7/VREF_7 IO_L27P_7 IO_L27N_7
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Pin Number T36 W32 W33 R41 R42 P40 R40 V36 V37 R38 R39 P38 R37 V34 V35 P41 P42 P36 P37 V32 V33 M41 N41 N39 N40 U35 U36 N36 N37 M39 M40 U32 U33 M37 M38 L37 M36
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 282
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L26P_7 IO_L26N_7 IO_L25P_7 IO_L25N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7/VREF_7 IO_L21P_7 IO_L21N_7 IO_L20P_7 IO_L20N_7 IO_L19P_7 IO_L19N_7 IO_L18P_7 IO_L18N_7 IO_L17P_7 IO_L17N_7 IO_L16P_7 IO_L16N_7/VREF_7 IO_L15P_7 IO_L15N_7 IO_L14P_7 IO_L14N_7 IO_L13P_7 IO_L13N_7 IO_L12P_7 IO_L12N_7 IO_L11P_7 IO_L11N_7 IO_L10P_7 IO_L10N_7/VREF_7 IO_L09P_7 IO_L09N_7 IO_L08P_7
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Pin Number V31 U31 L41 L42 K40 L40 T34 T35 L38 L39 K36 L36 T32 T33 K41 K42 K37 K38 R34 R35 H42 J41 J39 J40 R32 R33 J36 J37 H40 H41 T31 R31 H38 H39 H36 H37 P34
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 283
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L08N_7 IO_L07P_7 IO_L07N_7 IO_L72P_7 IO_L72N_7 IO_L71P_7 IO_L71N_7 IO_L70P_7 IO_L70N_7/VREF_7 IO_L69P_7 IO_L69N_7 IO_L68P_7 IO_L68N_7 IO_L67P_7 IO_L67N_7 IO_L66P_7 IO_L66N_7 IO_L65P_7 IO_L65N_7 IO_L64P_7 IO_L64N_7/VREF_7 IO_L63P_7 IO_L63N_7 IO_L62P_7 IO_L62N_7 IO_L61P_7 IO_L61N_7 IO_L84P_7 IO_L84N_7 IO_L83P_7 IO_L83N_7 IO_L82P_7 IO_L82N_7/VREF_7 IO_L81P_7 IO_L81N_7 IO_L80P_7 IO_L80N_7
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Pin Number N35 G41 G42 G39 G40 P32 P33 F38 G38 F37 G37 N32 N33 G35 G36 F41 F42 P31 N31 E41 F40 E36 F36 M34 M35 E35 F35 D40 E40 L34 L35 D39 E39 D38 E37 K34 J35
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 284
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L79P_7 IO_L79N_7 IO_L78P_7 IO_L78N_7 IO_L77P_7 IO_L77N_7 IO_L76P_7 IO_L76N_7/VREF_7 IO_L75P_7 IO_L75N_7 IO_L74P_7 IO_L74N_7 IO_L73P_7 IO_L73N_7 IO_L06P_7 IO_L06N_7 IO_L05P_7 IO_L05N_7 IO_L04P_7 IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 Pin Number D41 D42 C39 C40 H34 H35 C37 D36 B38 C38 F34 G34 C35 C36 A39 B39 D34 D35 A37 B37 A36 B36 B34 C34 A35 B35 XC2VP100
7 7 7 7 7 7 7 7 7 7
VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7
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W39 P39 K39 F39 D37 W35 P35 K35 M33 H33
DS083 (v4.7) November 5, 2007 Product Specification
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 Pin Description VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_5
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Pin Number AA29 Y29 W29 V29 U29 T29 R29 AA28 Y28 W28 V28 U28 T28 AU39 AN39 AJ39 AD39 AW37 AN35 AJ35 AD35 AR33 AL33 AH29 AG29 AF29 AE29 AD29 AC29 AB29 AG28 AF28 AE28 AD28 AC28 AB28 AW33
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 286
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 Pin Description VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3
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Pin Number AL30 AW29 AR29 AJ26 AW25 AR25 AJ25 AH25 AJ24 AH24 AJ23 AH23 AJ22 AH22 AJ21 AH21 AJ20 AH20 AJ19 AH19 AW18 AR18 AJ18 AH18 AJ17 AW14 AR14 AL13 AW10 AG15 AF15 AE15 AD15 AC15 AB15 AH14 AG14
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 287
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2
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Pin Number AF14 AE14 AD14 AC14 AB14 AR10 AL10 AN8 AJ8 AD8 AW6 AU4 AN4 AJ4 AD4 AA15 Y15 W15 V15 U15 T15 AA14 Y14 W14 V14 U14 T14 R14 M10 H10 W8 P8 K8 D6 W4 P4 K4
XC2VP100
DS083 (v4.7) November 5, 2007 Product Specification
Module 4 of 4 288
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 -- XC2VP100 No Connects Bank 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description VCCO_2 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 Pin Number F4 R21 P21 R20 P20 R19 P19 R18 P18 H18 D18 P17 H14 D14 M13 D10 D33 M30 H29 D29 P26 R25 P25 H25 D25 R24 P24 R23 P23 R22 P22 XC2VP100
N/A N/A N/A N/A N/A
CCLK PROG_B DONE M0 M1
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AM10 J33 AN10 AP33 AN33
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN Pin Number AM33 K10 M32 M11 L10 AP10 K33 J10 M12 M31 L33 XC2VP100
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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AK30 N30 AJ29 P29 AJ28 AH28 R28 P28 AJ27 AH27 AG27 AF27 AE27 AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 P27 AH26
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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Pin Number AG26 AF26 U26 T26 R26 AG25 T25 AG24 T24 AG23 T23 AG22 T22 AG21 T21 AG20 T20 AG19 T19 AG18 T18 AH17 AG17 AF17 U17 T17 R17 AJ16 AH16 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX
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Pin Number W16 V16 U16 T16 R16 P16 AJ15 AH15 R15 P15 AJ14 P14 AK13 N13 BA42 AY42 AL42 AB42 AA42 M42 C42 B42 BB41 A41 BB40 A40 BB31 A31 BB22 A22 BB21 A21 BB12 A12 BB3 A3 BB2
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number A2 BA1 AY1 AL1 AB1 AA1 M1 C1 B1 AV42 AP42 AK42 AF42 AC42 Y42 U42 N42 J42 E42 BA41 AY41 C41 B41 BA40 B40 BB38 AV38 AP38 AK38 AF38 AC38 Y38 U38 N38 J38 E38 A38
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number BB34 AV34 AP34 AK34 AF34 AC34 Y34 U34 N34 J34 E34 A34 AD31 W31 BB30 AV30 AP30 J30 E30 A30 BB26 AV26 AP26 AE26 AD26 AC26 AB26 AA26 Y26 W26 V26 J26 E26 A26 AF25 AE25 AD25
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number AC25 AB25 AA25 Y25 W25 V25 U25 AL24 AF24 AE24 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 M24 BB23 AV23 AP23 AF23 AE23 AD23 AC23 AB23 AA23 Y23 W23 V23 U23 J23 E23 A23 AF22 AE22
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number AD22 AC22 AB22 AA22 Y22 W22 V22 U22 AF21 AE21 AD21 AC21 AB21 AA21 Y21 W21 V21 U21 BB20 AV20 AP20 AF20 AE20 AD20 AC20 AB20 AA20 Y20 W20 V20 U20 J20 E20 A20 AL19 AF19 AE19
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number AD19 AC19 AB19 AA19 Y19 W19 V19 U19 M19 AF18 AE18 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 BB17 AV17 AP17 AE17 AD17 AC17 AB17 AA17 Y17 W17 V17 J17 E17 A17 BB13 AV13 AP13 J13
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pin Number E13 A13 AD12 W12 BB9 AV9 AP9 AK9 AF9 AC9 Y9 U9 N9 J9 E9 A9 BB5 AV5 AP5 AK5 AF5 AC5 Y5 U5 N5 J5 E5 A5 BA3 B3 BA2 AY2 C2 B2 AV1 AP1 AK1
XC2VP100
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Table 14: FF1696 -- XC2VP100 No Connects Bank N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND Pin Number AF1 AC1 Y1 U1 N1 J1 E1 XC2VP100
Notes: 1. See Table 4 for an explanation of the signals available on this pin.
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FF1696 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 10: FF1696 Flip-Chip Fine-Pitch BGA Package Specifications
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Revision History
This section records the change history for this module of the data sheet. Date 01/31/02 08/14/02 08/27/02 09/27/02 11/20/02 12/03/02 Version 1.0 2.0 2.1 2.2 2.3 2.4 Initial Xilinx release. Added package and pinout information for new devices. * * Updated SelectIO-Ultra information in Table 4. (Table deleted in v2.3.) Corrected direction for RXNPAD and TXPPAD in Table 4 (formerly Table 5). Revision
Corrected Table 2 and Table 3 entries for XC2VP30, FF1152 package, maximum I/Os from 692 to 644. Added Number of Differential Pairs data to Table 3. Removed former Table 4. Corrections in Table 4: * Reclassified GCLKx (S/P) pins as Input/Output, since these pins can be used as normal I/Os if not used as clocks. * Added cautionary note to PWRDWN_B pin, indicating that this function is not supported. Added and removed package/pinout information for existing devices: * In Table 1, added FG676 package information. * In Table 3, added FG676 package option for XC2VP20, XC2VP30, and XC2VP40. * In Table 12, removed FF1517 package option for XC2VP40. * Added FG676 package pinouts (Table 7) for XC2VP20, XC2VP30, and XC2VP40. * Added package diagram (Figure 3) for FG676 package. * * * * Added section BREFCLK Pin Definitions, page 5. Added clarification to Table 4 and all device pinout tables regarding the dual-use nature of pins D0/DIN and BUSY/DOUT during configuration. Added notation of "open-drain" to TDO pin in Table 4. The final GND pin in each of six pinout tables was inadvertently deleted in v2.5.1. This revision restores the deleted GND pins as follows: - Pin A1, Table 6, page 16 (FG456) - Pin AF26, Table 7, page 30 (FG676) - Pin AN34, Table 10, page 98 (FF1152) - Pin E1, Table 11, page 130 (FF1148) - Pin C38, Table 12, page 162 (FF1517) - Pin E1, Table 14, page 253 (FF1696) Table 4: Deleted Note 2, obsolete. There is only one GNDA pin per MGT. Table 4: Deleted pins ALT_VRP and ALT_VRN. Not used in Virtex-II Pro FPGAs. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, are released to Production status. Table 4, signal descriptions column: - For signals TDI, TMS, and TCK, added: Pins are 3.3V-compatible. - For signals M2, M1, M0, added: Tie to 3.3V only with 100 series resistor. No toggling during or after configuration. - For signal TDO, added: No internal pull-up. External pull-up to 3.3V OK with resistor greater than 200. Recompiled for backward compatibility with Acrobat 4 and above. No content changes.
01/20/03
2.5
05/19/03
2.5.1
06/19/03
2.5.3
08/25/03 12/10/03 02/19/04
2.5.5 3.0 3.1
* * * *
03/09/04 06/30/04
3.1.1 4.0
*
Merged in DS110-4 (Module 4 of Virtex-II Pro X data sheet). Added data on available Pb-free packages and updated package diagrams for affected devices.
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Date 11/17/04 03/01/05
Version 4.1 4.2 * * *
Revision Table 4: Added requirement to VBATT to connect pin to VCCAUX or GND if battery is not used. Table 3: Corrected number of Differential I/O Pairs for XC2VP30-FF1152 from 340 to 316. Table 4: Changed Direction for User I/O pins (IO_LXXY_#) from "Input/Output" to "Input/Output/Bidirectional".
06/20/05 09/15/05 10/10/05 03/05/07 11/05/07
4.3 4.4 4.5 4.6 4.7
No changes in Module 4 for this revision. No changes in Module 4 for this revision. No changes in Module 4 for this revision. * * Figure 2, page 29: Corrected NOTE 3. Figure 7, page 161: Updated with drawing showing correct heat sink profile and detail.
Updated copyright notice and legal disclaimer.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules: * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview (Module 1) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description (Module 2) * * Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics (Module 3) Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information (Module 4)
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